Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
980 Views

DE0-Nano-SoC Kit, Route ETH pins to FPGA?

Hello, 

 

Regarding Terasoc's product, http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=941 

 

I'm considering making a tiny little thing where Ethernet/UDP communication is time-critical, handled by the FPGA and not the HPS component. 

The DE0-Nano-SoC looks ideal, except I really dont need the ARM CPU... 

 

Does anyone know if the board supports routing the ENET pins to the FPGA directly? 

 

 

Grateful for any feedback on this, guys :) 

 

 

With Best Regards, 

Stride
Tags (1)
0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
88 Views

An update from Terasic support: 

 

thank you for your e-mail. 

 

the enth pins are connected to arm cpu pins, i am afraid it is impossible to modify the enth pins connection directly to the fpga. 

 

free to contact us if you have any other question. 

 

 

 

Hm, not cool :(
Altera_Forum
Honored Contributor I
88 Views

Since you don't require the ARM core, perhaps the DE2-115 is better suited for your needs? 

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=139&no=502&partno=2
Altera_Forum
Honored Contributor I
88 Views

 

--- Quote Start ---  

Since you don't require the ARM core, perhaps the DE2-115 is better suited for your needs? 

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=139&no=502&partno=2 

--- Quote End ---  

 

 

Thanks, I actually have one! 

 

It's a bit of an overkill for the solution tho. 

Basically I want to make a "no cpu" wirespeed UDP TX/RX chain for NTP, then feed "zero latency/jitter" data from a GPS. 

 

That tiny little DE0 device was almost perfect. Except for adding the HTS, CPU logic and the latence from it... 

 

Oh well. 

 

/Stride
Reply