I implemented Terasic's "My First FPGA" tutorial, and the 5Mhz PLL output is erratic.The project uses an ALTPLL to divide the onboard 50MHz oscillator down to 5MHz. I routed the clock to a GPIO and monitor with my logic analyzer. But the GPIO output wavers between 4 and 6 MHz (clock is high/low for: 83ns, 83ns, 1167ns, 83ns, 83ns, 1167ns, ...) I used the Megafunction Wizard to add the ALTPLL. My input is 50 MHz, output is 5 MHz, ratio 1/10, duty cycle 50%. All options are disabled (reset on loss of lock, etc). I'm routing to GPIO_10 / PIN_F13, if that matters. Am I missing something? I'm pretty confident in the Logic analyzer; 5MHz is well within its bandwidth. The jitter doesn't matter for LEDs, but now I'm trying to clock serial data into an IC on a breadboard, and it's become annoying. Thanks, Sean
Shouldn't happen. I would monitor PLL locked signal to get additional information.Self-reset at least won't hurt. I'm not absolutely sure how the PLL works without a global reset.