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Altera_Forum
Honored Contributor I
823 Views

DE0-Nano project has warning about interface voltages

I have a simple project created by the System Builder application included with my DE0-Nano. That application creates QPF, QSF, and SDC files as well as an example Verilog file. If I compile the project as-is (with the empty top-level module that declares some inputs and outputs) in Quartus II, I get the expected warnings about unused inputs and undriven outputs but I also get a warning that I don't know how to address. 

 

 

--- Quote Start ---  

Warning (169177): 7 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. 

--- Quote End ---  

 

 

I get this warning for all of the inputs. I'm pretty sure I'm getting this because the System-Builder-created QSF file contains several instance assignments for the 3.3v LVTTL I/O standard. Here's an example. 

 

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW 

 

I took a look at an 447 (http://www.altera.com/literature/an/an447.pdf) as suggested here (https://www.alteraforum.com/forum/showthread.php?t=23806), but it's utterly opaque to me. I'm assuming TerasIC adhered to that application note when creating the board and that it's safe to ignore this warning, but I'd like to get rid of it. 

 

Are there some additional instance assignments I can use to address this warning?
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Altera_Forum
Honored Contributor I
52 Views

AFAIK you always get this warning, as long as you are using 3.3/3.0/2.5-V I/O standards. There is no way to get rid of it.

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