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Altera_Forum
Honored Contributor I
1,095 Views

DE0 SDRAM Access

Hello :) 

 

First time FPGA user here. I'm a University student currently working on a project using a DE0 dev board. I've spent a good hour poking around on these forums trying to find what I'm looking for, but I aplogise in advance if I've missed the information I'm looking for! 

 

I want to write and read from the boards external RAM chip. There appears to be documentation/tutorials kicking about, but it relates to using NIOS/SOPC builder. This project is totally written from scratch in SystemVerilog, so that is of little use to me. 

 

I'm happy writting my own SDRAM controller, however, I don't quite understand the whole rows/columns signal thing. I effectively want to abstract the SDRAM such that I only have to worry about the address, data and write enable signals - the same way I treat the embedded M9K blocks. Does anyone have any example code or know of a tutorial they can point me towards? Or perhaps someone could shed some light on the whole rows/columns business? 

 

Cheers
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5 Replies
Altera_Forum
Honored Contributor I
58 Views

Hi Jacki2ya: 

 

The Bank/Row/Column addressing scheme of drams/ sdrams is basically a way to reduce the number of pins required when accessing the ram. 

 

Since the ram is a Dynamic Ram based design, there are different rules associated with opening banks, and refreshing the ram that need to be followed. If you truly want to write your own controller, I suggest you download the zentel datasheet for the ram, and start going through the timing diagrams, and understanding the ram chip. 

 

Otherwise, you can you an SOPC/QSYS ram controller from the example system, and just create you own "Avalon" master to control the ram directly, by cutting the appropriate parts out of the system and tying it to your own master. 

 

The Avalon bus system is simpler than SDRAM controller, and closer to what you want in terms of address the ram, but either way you are writing code to talk to a standard interface, that you will have to read the datasheet/specification to understand.  

 

If you want to talk directly to the Zentel ram, go to the Zentel website, and download the spec for the ram device in on the DE0 board. 

 

If you want to try the Avalon approach, search on google for Avalon Bus Specification, and download the spec. 

 

Pete
Altera_Forum
Honored Contributor I
58 Views

Hi Pete, 

 

Thank you for your reply. I struggled for a bit with the Avalon stuff and the SDRAM, so i've switched to using the Flash Memory instead. Thanks for the advice anyway :)
Altera_Forum
Honored Contributor I
58 Views

hi jacki2ya... 

 

my situation is exactly similar to yours, I also wanted to access the SRAM on board, without involving NIOS/SOPC builder. I was struggling in this situation for weeks already, still can't find a proper solution... i'm working on a project using DE2. I guess it's more or less similar... 

 

Can you provide some advice? Why are you switching to Flash? It's easier to access?
Altera_Forum
Honored Contributor I
58 Views

I'd recommend checking the datasheet for the flash chip (I'm not familiar with the DE2 board). 

 

Atleast on the DE0 board, the flash is a lot more straight forward to access (you don't have to worry about column/row signals). It's access times are slower though (70/90ns) and from what I gathered you have to read/write sectors in one go. 

 

I'm using this to debug my project (it's signal processing) by downloading data onto the flash using the control panel, processing it on the FPGA, then downloading the results back through the control panel for analysis. I haven't yet written any code (trying to get the EDA tools working first!) but will post back here if/when I do.
Altera_Forum
Honored Contributor I
58 Views

i see...i guess mine is more or less the same also...involving writing data to the memory, process, then write back the results... 

 

Well, hope there are good news soon... :) thanks for your feedback ya..... :)
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