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DE0-nano - Cyclone IV and custom SDRAM on-board contoller

Honored Contributor II



I have been trying to find an approach of communicating with the on-board Synchronous DRAM (Non-DDR) IS45S16160G WITHOUT a soft core Nios II CPU. My intention is to store ADC data for later processing within the FPGA or a MCU. The DRAM suits my needs, in terms of capacity 16Mx16bits, for storing 16bits values (even though other values can be stored as well!) from 2 parallel ADCs probably connected with LVDS levels at 100-150Msamples/sec. I am troubled as far as the memory handling is concerned. I have just started working with Verilog (will be studying for a long time though) and at this point i am mostly trying to discover how everything works in Quartus. I have succesfully worked with the RTL modelsim and the SignalTap analyser. I have succesfully designed my own controller for the ADC on-board the DE0-nano (attached). However, when it comes for the DRAM on the DE0-nano things are much more complicated and i was wondering how i can use the DRAM to start storing values from the ADC on-board DE0-nano and later by connecting a high speed 100-150Msps eval board and storing data to the DRAM. My understanding is that the RAM controllers (ALTMEMPHY) in the Megawizard are the ones that physically interfere between the memory chip and the user code thus giving R/W access. Later i discovered that Altera has some downloadable mem-access verilog templates for letting users accessing memory (burst/pipeline) from their own custom logic / modules. How does this work? Do these verilog templates connect to the ALTMEMPHY mem controller and such grand access to the memory chip? I know these are pretty basic things but i have been struggling with various memory-controller-related stuff like SDRAM manuals, pdfs containing studies of custom HDL controllers and even looked at the JEDEC website. All i can remember are things like ACTIVE, PRECHARGE etc and probably some of the basic stuff that a DRAM / DDR ram chip does. I am a little lost and looking for some guidance before i lose my interest on the project i have commited doing (http://www.youtube.com/watch?v=73ygbq9wq_m). I am almost sure that i could start writing my own custom mem controller if i only knew the exact way that the DRAM on board the DE0-nano works. I really do not know where to start from although Altera's documentation seems fantastic in terms of size and quality. I haven't still found a guide to help me getting started the proper way and eventually show me the way to other resources that will help me with this memory-interface related issue. 


Hoping that someone could give me some guidelines.  


Thanks for your time reading this. 



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