I think this is the right forum for this, because it involves several different components.Basically I am having the same problem many people on this forum seem to have had, but I have had no luck getting it to work. I have an Altera Cyclone II FPGA starter board (basically a DE1) board. I am trying to get the SDRAM to work when using NIOS II and SOPC builder. I have instantiated the SDRAM controller, configured it as explained in the 'Using the SDRAM Memory on ALtera's DE1 Board With VHDL Design' altera tutorial, and created the PLL. I have a PLL with two outputs, one the undisturbed 50Mhz clock passed through, and the other phase shifted by -3.00ns. I still get the same same error on downloading: Verifying failed between address 0x800000 and 0x801CC7 I have tried using different phase shifts up and down, I have tried only connecting the phase shifted clk to the PLL, and keeping the system clock from the 50Mhz input and not from the PLL. Nothing seems to work. Seems most people on the forum got it to work by using the two clock PLL as described in the above tutorial, but it is not working for me. Any help greatly appreciated as I am a s/w engineer so this is all a little new to me! Thanx
This could happen alot of different things. I remember SDRAM phase shift from -2.5 to 4.0 ns in PLL. But the default is -0.75 ns.1. Pins assigment set incorrect. 2. Reset_n and Clock assignment different pins. 3. Incorrect SDRAM in SOPC builder. If all of these things are correct. You don't see the failed in NIOS. It's good you post your design Quartus, SOPC Builder configure. Best regards, Sean
Ok, I have checked all the things I can think of or have come across in the forums and I am still having no luck.What do I need to post exactly for someone to figure out what it is I am doing wrong? (And how do I upload them as I don't see a file upload on the editor). Thanks.
hi, I've been running through the same problem.I'm using DE2-115 and tried to use SDRAM in my project (currently just a test project, including only NIOS II Processor, Jtag-UART, and SDRAM Cotroller). I tried to use PLL to manually set the clock signals, instead of using the IP provided by the altera university program as in the tutorial. I think you should set the clock signal connected to niosII processor to be phase shift (-3.0ns) and connect to undisturbed signal to DRAM_CLK. I got no verification error in this way. (I'm a newbie here, correct me if i"m wrong) But when try to run some simple C program through NIOS2EDS, no output can be shown. And also I've problems set the clock signals to a higher frequency, still searching for solutions :(