DE1 SoC hangs when programmed

[Altera_Forum]

Hi! 

 I have made a small program to make a led flicker and programmed the FPGA with it. Everything went fine. However I have another project which I used to build in a previous version of quartus II and program it on an older cyclone II FPGA. I build this same project with the newer quartus II version 17.1 with no errors. However, when I try to program the cyclone V the following happens: the process starts properly, reaches 86% and then fails. After that I have to power off and on the FPGA so that it works again.  Any idea would be appreciated. Thank you.

[Altera_Forum]

Is the project targeting the correct device on your board? Did you adjust the pin assignments in the Pin Planner?

[Altera_Forum]

--- Quote Start ---  Is the project targeting the correct device on your board? Did you adjust the pin assignments in the Pin Planner?  --- Quote End ---    Yes, sure! Actually I am not that beginner. I have worked quite a lot with FPGAs.   It used to give me a warning saying that the write logic was disabled. I rewrote my ram file and the warning dissapeared. I have also a warning stating the following:   Warning (332060): Node: counter2 was determined to be a clock but was found without an associated clock assignment.  Info (13166): Register \process_1:cnt[0] is being clocked by counter2  Anyway, the project used to work on older software/hardware versions so I do not believe that the problem is related to code.  I got it to work fixing the warning about the ram. However it only works under restricted parameter's values, so there is still something missing...  Thanks.