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Altera_Forum
Honored Contributor I
1,406 Views

DE10-Lite System Builder

Trying to get a zero warning build of a simple project generated by the Terasic System Builder for a minimal system.. 

http://www.alteraforum.com/forum/attachment.php?attachmentid=13135&stc=1  

Just the clocks and the LEDRs and the Switches.  

1) Generate the project, then double click on .qpf file in the CodeGenerated/DE10_Lite/ folder. 

2) To eliminate the no project file defined, add the *.v file to the current project, add/remove files to project and select the .v file. 

2) To eliminate a warning on the number of processors being used by the software, select the Compilation Process Settings: 

http://www.alteraforum.com/forum/attachment.php?attachmentid=13136&stc=1  

3) To eliminate the I/O Pins only partially specified warning, launch the pin planner and set the current strength on the output pins, (I have been unable to assign the pins all to a minimum current, or all to the maximum and eliminate the warning, at least one needs to be a different value from the others, any suggestions?) 

http://www.alteraforum.com/forum/attachment.php?attachmentid=13137&stc=1  

4) The minimum Verilog code simply sets the output to the input on the rising edge of a clock: 

http://www.alteraforum.com/forum/attachment.php?attachmentid=13138&stc=1  

5) Delete the ADC_CLK_10 and MAX10_CLK2_50 clocks (not used in the code) to eliminate the inputs drive no logic warnings. (I closed the project and commented them out in the *.sdc and the *.qsf files, you can also delete them through the Pin Planner by clicking right on the pin name, edit and delete) 

6) The resulting builds with two warnings. Which are 

>> Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. 

and 

>> Warning (169177): 11 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. 

 

I haven't been able to get rid of the LogicLock warning, it seems the Lite Edition seems to sets options which causes the warning in the .qsf file?? 

 

The second warning (is normal) always occurs?? 

 

Don't like to turn off warnings, but would like a clean (no warning) synthesis. 

 

 

Joel
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
168 Views

Hello, 

 

There is a thread on this forum with the title "LogicLock warning". 

This thread explains that it is something to live with unless you purchase Quartus II. 

 

Best regards, 

Johi.
Altera_Forum
Honored Contributor I
168 Views

Johi, 

 

Thanks for the reference.  

 

I clicked right on the warning and suppressed the message.... since we can't launch the logiclock tools anyway.  

 

I will leave the warning which directs the user to reference to AN447 on, since it is a good thing to check. 

 

Thanks again. 

 

Joel