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Honored Contributor I

DE10-Nano Kit vs DE0-Nano-SoC Kit/Atlas-SoC Kit : Which to procure?

Background : I have no prior experience in FPGA SoC or FPGA or CPLD however I have worked extensively on Raspberry Pi 3 Model B (Raspbian OS) and ARM M4 micro-controller (Bare Metal Programming). 


I have a difficulty choosing between DE10-Nano Kit vs DE0-Nano-SoC Kit/Atlas-SoC Kit. All the difference I could find is in SoC and HDMI which is only output present in DE10-Nano Kit. 

The difference I found out in SoC was 110K Logic Element (DE10-Nano Kit) vs 40K Logic Element (DE0-Nano Kit) and presence of 1 hard memory controller (DE0-Nano Kit) against no hard memory controller (DE10-Nano Kit). I have no idea how any of this will affect me and what would be their implications. 


I plan to use Verilog HDL due to its relatedness to C/C++ (which I am familiar with). 

I ultimately plan use this board fuzzy logic controller implementation, machine learning and machine vision. 

I request experts to guide me in selection of appropriate board.
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Honored Contributor I

The DE10-Nano kit has a hard memory controller. I don't know if these boards will work for your applications, but unless you don't want the HDMI or are cost-constrained, I would probably go with the higher capacity FPGA on the DE10-Nano. The DE0 has a slightly faster ARM CPU complex than the DE10 (925Mhz vs. 800Mhz). 


I am going through the DE10-Nano documentation with my board and it seems pretty straight-forward so far. I have gotten some of the FPGA demonstrations to work, and have compiled/run C code on the board under Linux.
Honored Contributor I


Honored Contributor I

That's interesting; at this link they say the DE10 part has one hard memory controller in the lower right corner: 


Whereas for the DE0 part, it shows two controllers (N suffix does not work): 


I could be wrong, but I get the impression that there is always a hard memory controller inside the Cyclone V HPS,  

and there are optional hard memory controllers outside of the HPS based on the particular part. 


From the Cyclone V device overview: 

"Cyclone V devices support up to two hard memory controllers for DDR3, DDR2, and LPDDR2 SDRAM 

devices. Each controller supports 8 to 32 bit components of up to 4 gigabits (Gb) in density with two chip 

selects and optional ECC. For the Cyclone V SoC devices, an additional hard memory controller in the 

HPS supports DDR3, DDR2, and LPDDR2 SDRAM devices." 


In Table 10 of the same document, it lists the SE max resource count of the FPGA hard memory controller  

from the HPS hard memory controller in separate rows. 


If this interpretation is correct, then perhaps the SE device part selector in Cyclone V device overview  

manual refers to the number of hard memory controllers outside of the HPS, and the web link above that 

I reference describes the total number of hard memory controllers inside the entire part.