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Altera_Forum
Honored Contributor I
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DE10-Nano OpenCL examples compilation with Quartus Prime and OpenCL SDK 17.1

Hello. 

 

During "boardtest" example compilation from DE10_Nano_OpenCL.pdf with Quartus Prime and OpenCL SDK 17.1 I have the next exceptions:  

 

E:\intelFPGA\17.1\hld\board\terasic\de10_nano\examples\boardtest>aoc device/boardtest.cl -o bin/boardtest.aocx --board de10_nano_sharedonly --reportWarning: Please use -board=<value> instead of --board <value> Warning: Please use -report instead of --report aoc: Selected target board de10_nano_sharedonly aoc: Running OpenCL parser.... e:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/device/boardtest.cl:77:20: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance __global uint *dst, ^ e:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/device/boardtest.cl:78:26: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance __global const uint *index, ^ 2 warnings generated. aoc: Optimizing and doing static analysis of code... !=========================================================================== ! The report below may be inaccurate. A more comprehensive ! resource usage report can be found at boardtest/reports/report.html !=========================================================================== +--------------------------------------------------------------------+ ; Estimated Resource Usage Summary ; +----------------------------------------+---------------------------+ ; Resource + Usage ; +----------------------------------------+---------------------------+ ; Logic utilization ; 38% ; ; ALUTs ; 22% ; ; Dedicated logic registers ; 18% ; ; Memory blocks ; 32% ; ; DSP blocks ; 0% ; +----------------------------------------+---------------------------; Compiling for FPGA. This process may take a long time, please be patient. Error (10759): Verilog HDL error at boardtest_system.v(615): object kernel_receiver_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 615 Error (10112): Ignored design unit "kernel_receiver_partition_wrapper" at boardtest_system.v(589) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 589 Error (10759): Verilog HDL error at boardtest_system.v(844): object kernel_sender_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 844 Error (10112): Ignored design unit "kernel_sender_partition_wrapper" at boardtest_system.v(817) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 817 Error (10759): Verilog HDL error at boardtest_system.v(1096): object mem_read_writestream_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1096 Error (10112): Ignored design unit "mem_read_writestream_partition_wrapper" at boardtest_system.v(1050) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1050 Error (10759): Verilog HDL error at boardtest_system.v(1367): object mem_readstream_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1367 Error (10112): Ignored design unit "mem_readstream_partition_wrapper" at boardtest_system.v(1321) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1321 Error (10759): Verilog HDL error at boardtest_system.v(1626): object mem_writestream_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1626 Error (10112): Ignored design unit "mem_writestream_partition_wrapper" at boardtest_system.v(1592) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1592 Error (10759): Verilog HDL error at boardtest_system.v(1861): object nop_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1861 Error (10112): Ignored design unit "nop_partition_wrapper" at boardtest_system.v(1839) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1839 Error (10759): Verilog HDL error at boardtest_system.v(2116): object reorder_const_finish declared in a list of port declarations cannot be redeclared within the module body File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2116 Error (10112): Ignored design unit "reorder_const_partition_wrapper" at boardtest_system.v(2059) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2059 Error (10112): Ignored design unit "kernel_receiver_top_wrapper_0" at boardtest_system.v(2352) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2352 Error (10112): Ignored design unit "kernel_sender_top_wrapper_0" at boardtest_system.v(2427) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2427 Error (10112): Ignored design unit "mem_read_writestream_top_wrapper_0" at boardtest_system.v(2506) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2506 Error (10112): Ignored design unit "mem_readstream_top_wrapper_0" at boardtest_system.v(2623) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2623 Error (10112): Ignored design unit "mem_writestream_top_wrapper_0" at boardtest_system.v(2740) due to previous errors File: E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2740 Error: Quartus Prime Analysis & Synthesis was unsuccessful. 19 errors, 2 warnings Error (293001): Quartus Prime Full Compilation was unsuccessful. 21 errors, 2 warnings Error: Flow compile (for project E:/intelFPGA/17.1/hld/board/terasic/de10_nano/examples/boardtest/bin/boardtest/top) was not successful Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. Error (23031): Evaluation of Tcl script e:/intelfpga/17.1/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 28 errors, 2 warnings Error: Compiler Error, not able to generate hardware  

 

How I can fix this exception or how I can receive free test license for OpenCl v.16.1 for testing? 

Link to DE10-Nano resources, BSP(Board Support Package) for Intel FPGA SDK OpenCL 16.1: http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=165&no=1046&partno=4 

 

Thanks.
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2 Replies
Altera_Forum
Honored Contributor I
226 Views

I have the same problem

Robert_Duan
Beginner
226 Views

I've same problem. Any update???

kernel_receiver_finish_declared re-declared in boardtest_system.v, which is generated by aoc. Any internal problem?

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