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DE10-Nano burning via JTAG J8 external blaster and PCB Layout schematic

IOzan
New Contributor I
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Hello,

 

I have been working with the DE10-nano card for a while. I have two questions that require your attention:

 

  1. I want to burn to the FPGA and EPCS64 (.sof and .jic files) via the J8 connector that I assembled (and an external USB Blaster). I prepared the .jic file according to the User manual (Chapter and via the J13 connector I manage to burn it successfully (MSEL[4-0]=10010). Now I change J13 to J8 and then it fails to burn. What could be the problem? Is there any manual that explains how to burn the FPGA from an external Blaster via the J8 connector?
  2. I want to try to debug the DDR3 so from the electrical diagram I cannot see all the test Points located next to it. Is it possible to get the PCB layout files for the card? (any viewer will do just fine).

 

Thanks a lot,

Idan,

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Fakhrul
Employee
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Hi,


To burn the FPGA and EPCS64 via the J8 connector, you should check the pin assignments, MSEL settings, power supply, grounding, and cable quality, as J8 may have different requirements than J13. Reviewing the DE10-Nano schematic and user manual can help identify the correct configurations, and you may find further assistance from Terasic forums or support. You can refer, DE10-Nano User Manual.

For debugging DDR3, you can trace signals using the schematic and tools like logic analyzers or oscilloscopes. PCB layout files are typically not available, but you can reach out to Terasic support to inquire about access to layout diagrams or a simplified viewer for debugging.


Hope this helps!


Regards,

Fakhrul


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Fakhrul
Employee
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As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.


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