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Altera_Forum
Honored Contributor I
1,144 Views

DE2-115 Demo not compiling Q16 "Pha..select has width 4 in tcl, but 3 in design file"

Hello everybody, 

 

I have a DE2-115, and i am trying to port my working application from my DE0-CV. 

 

If i try to compile the "DE2_115_NIOS_HOST_MOUSE_VGA demonstration from the Terrasic cd (downloaded even last version) in QSYS, i get. 

 

"Error: Port Phasecounterselect has Width 4 in TCL, but 3 in the design file" 

 

If i make a new instance of th PLL i get indeed (file DE2_115_SOPC_pll.v) .phasecounterselect({3{1'b0}})

 

Whereas a newly generated Pll in quartus shows: .phasecounterselect ({4{1'b1}}), 

 

Any comments would be appreciated. 

 

Best Regards, 

Johi. 

 

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4 Replies
Altera_Forum
Honored Contributor I
97 Views

 

--- Quote Start ---  

Hello everybody, 

 

I have a DE2-115, and i am trying to port my working application from my DE0-CV. 

 

If i try to compile the "DE2_115_NIOS_HOST_MOUSE_VGA demonstration from the Terrasic cd (downloaded even last version) in QSYS, i get. 

 

"Error: Port Phasecounterselect has Width 4 in TCL, but 3 in the design file" 

 

If i make a new instance of th PLL i get indeed (file DE2_115_SOPC_pll.v) .phasecounterselect({3{1'b0}})

 

Whereas a newly generated Pll in quartus shows: .phasecounterselect ({4{1'b1}}), 

 

Any comments would be appreciated. 

 

Best Regards, 

Johi. 

 

 

--- Quote End ---  

 

 

 

The error might have something to do with the Quartus II version. The demonstrations in Terasic's CD-ROM is for Quartus II 11.1 SP2 version.  

You used Quartus 16.0 to compile; from Quartus II 11.1 SP2 to Quartus II 16.0, I thought it's because of the widely across gap between the two versions. Due to compatibility issue, IP cannot be updated directly.  

You may try to cancel PLL IP and change a new PLL IP to have a try again.
Altera_Forum
Honored Contributor I
97 Views

Hello Barbara, 

Thank you for the answer. 

I downgraded to version 13.1 a week ago and the error is no longer there. 

Fact remains that i think there is an error in the system code that reveals itself in Quartus 16. 

The parameters in the .v and in the .tcl codes should match. 

The .phasecounterselect bits have to do with a hardware interface in the pll, this can only have 3 or 4 bits, but not the both. 

It is also a fact that in the wizzard, some counts are started from 0, ohters from 1, so it could be likely that this led to confusion. 

It could be that somenone else could shed a more detailed opinion about this,  

with my limited knowledge i have the impression this could be an altera bug? 

Best Regards, 

Johi
Altera_Forum
Honored Contributor I
97 Views

I encountered this as well. It seems to be a bug as reported here: 

http://ftp.beckhoff.com/download/document/io/ethercat-development-products/ethercat_ipcore_datasheet...
Altera_Forum
Honored Contributor I
97 Views

To resolve this error, follow the steps that are highlighted in the previous addendum. I copied them here for easier reference: 

1. Open <Quartus installation folder>\16.0\ip\altera\sopc_builder_ip\altera_avalon_altpll\altera_avalon_altpll_hw.tcl 

2. On row 339, change the line to: 

if { $device_family == "MAX10" || $device_family == "MAX 10" || $device_family == "cyclone iv e"}

 

3. Close Quartus, then relaunch Quartus again. 

4. Open Qsys and regenerate the .qsys file. The error should go away
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