DE2-115/ RS-232 Broken Communication

Losspost · ‎12-05-2018

Hi.

I am currently trying to communicate via pc to my FPGA Board. In the Simulation the Data Transmission works fine. But when I try to send Data to the real Board the Data doesnt make any sense at all. Even with the same data input to the board, i get different outputs from the FPGA Board. Anyone can help me?

My Code:

module UART(clk,uart_rxd,uart_txd,uart_cts,uart_rts,led_out);
 
 
 
	input clk;
	input uart_rxd;
	output uart_txd;
	//Clear to send
	inout uart_cts;
	//Request to send;
	inout uart_rts; 
	
	output[7:0] led_out;
	
	
	//8 times the Baud Freq.
	localparam baud_counter_value = 5208/8;
	//localparam baud_counter_value = 2500000;
	reg[14:0] baud_counter;
	//BaudClock
	reg baud_clock_reg;
	wire baud_clock;
	//Inital CTS/RTS register
	reg cts;
	reg rts;
	
	//Data Register
	reg[7:0] data;
	reg txd;
	
	//LED Test Register
	reg[7:0] led;
	
	//Counter
	reg[32:0] counter;
	
	
	//Uart State Register
	localparam
		s_IDLE = 0,
		s_DELAY = 1,
		s_DELAY_RESET =2,
		s_SEND = 3,
		s_RECEIVE = 4,
		s_TEST = 5,
		s_RECEIVE_DELAY_RESET=6,
		s_CLEAN_UP=7;
		
	reg[4:0] state_uart;
		
	//Baud Delay Counter
	//Because baud_clock is baud_clock * 8. We have to wait 8 baud_clocks for 1 baud bid at 9600baud/s
	reg baud_delay;
	reg[4:0] baud_delay_counter;
	reg delay;
	
	initial begin
		//Initialize Baud Clock
		baud_clock_reg = 0;
		baud_counter = 14'b0;
		cts = 0;
		rts = 0;
		data = 8'b0;
		led = 8'b00000001;
		counter = 0;
		baud_delay = 0;
		baud_delay_counter = 4'b0;
		//Inital state
		state_uart = s_IDLE;
		
	end
	
//Creating a Baud Clock Baudrate = 9600	
/*-------------------------------------------------------------------*/			
	always@(posedge clk) begin
		
		if(baud_counter == baud_counter_value-1) begin
			baud_clock_reg <= !baud_clock_reg;
			baud_counter = 0;
		end else begin
			baud_counter <= baud_counter +1;
		end
	
	end	
	
 
/*-------------------------------------------------------------------*/
//Baud Delay Counter
/*-------------------------------------------------------------------*/
	always@(posedge baud_clock && baud_delay == 1) begin
		case(state_uart)
			s_DELAY: begin
				baud_delay_counter <= baud_delay_counter +1;	
				if(baud_delay_counter == 4) begin
					baud_delay_counter <= 0;
				end
			end
			s_RECEIVE: begin
				baud_delay_counter <= baud_delay_counter +1;
				if(baud_delay_counter == 8) begin
					baud_delay_counter <= 0;
				end
			end
			s_DELAY_RESET: baud_delay_counter <= 0;
			s_RECEIVE_DELAY_RESET: baud_delay_counter <=0;
		endcase
		
	end
 
 
/*-------------------------------------------------------------------*/			
//Getting Request from PC to receive Data
/*-------------------------------------------------------------------*/			
	always@(posedge clk) begin
	
		case(state_uart) 
		
			s_IDLE: begin
				//If Host Request to send Data
			
				//Waiting for start bit
				if(uart_rxd == 0) begin
					
					state_uart <= s_DELAY;
				end
			end
			
			s_DELAY: begin
				
				//Wait for 4 Baud Ticks to "sample Data"
				if(baud_delay_counter == 4) begin
					baud_delay <= 0;
					state_uart <= s_DELAY_RESET;
					
				end 
				//Activate Baud Counter
				baud_delay <= 1;
				
				
			end
			
			s_DELAY_RESET: begin
				if(baud_delay_counter == 0) begin
					state_uart <= s_RECEIVE;
				
				end
			end
			//Receive the Data
			s_RECEIVE: begin
				//Waiting for one "real" baud tick
				baud_delay <= 1;
				if(baud_delay_counter == 8) begin
					//Setting Least Significant Bit
					data[0] = uart_rxd;
					txd <= uart_rxd;
					//Shift 0 bit one to the Left 
					//= because its only getting executed after the previous line was executed
					
					//Dont Shift the Last Bit
					if(counter != 7) begin
						data = data << 1;
					end
					counter = counter + 1;
					state_uart <= s_RECEIVE_DELAY_RESET;
				end
				
				if(counter == 8) begin
					baud_delay <= 0;
					state_uart <= s_TEST;
	
				end
			end
			
			s_RECEIVE_DELAY_RESET: begin
				if(baud_delay_counter == 0)begin
					state_uart <= s_RECEIVE;
				end
			end
			
			s_TEST: begin
				led <= data;
			
				state_uart <= s_CLEAN_UP;
	
			
			end
			s_CLEAN_UP: begin
				data = 8'b0;
				counter = 0;
				txd <= 1;
				state_uart <= s_IDLE;
			end
		endcase
		
	end
 
/*-------------------------------------------------------------------*/			
 
 
	//Update Baud Clock Signal
	assign baud_clock = baud_clock_reg;
	assign uart_cts = cts;
	assign uart_rts = rts;
	assign led_out = led;
	assign uart_txd = txd;
 
 
endmodule

JohnT_Intel · ‎12-06-2018

Hi,

I would recommend you to try the refence design from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=163&No=502&PartNo=4 to confirm if there is any issue on the board or your design.