Attempting to add some custom FPGA code to template based on Web Server demonstration code. Am new to FPGA development. In attempt to use something that I know already works (have executed this successfully), I made a copy of the ledr.v file and renamed it to Myledr.v. Then, using ComponentBuilder, I created a MyLEDR componenet and added the MyLedr.v file. When I analyze the component, the pop-up indicates that there are 0 errors and 0 warnings. However, the dialog at the bottom of the ComponenetEditor gives an error that out_port[18] must be a multiple of a symbol with 8. This also shows up in SOPC Builder.
Since this is based on a known good .v file (all I changed was the module name), why would out_port [17:0] be ok in the template, but not in my file?
Thanks, in advance.....
