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DE2-115 : position of data pin of FLASH and SDRAM

Altera_Forum
Honored Contributor II
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Hi, 

 

I have a DE2-115 and I try to understand how memories are interfaced. In the "External Memory Interface in Cyclone IV Devices" book I read : 

Cyclone IV devices use data (DQ), data strobe (DQS), clock, command, and address pins to interface with external memory. 

But I noticed that some of the data pin of the FLASH and SDRAM are connected to simple I/O of the FPGA (DQ4, DQ10, ...). So I wonder if this is a problem that I use standard I/O for the data pin in the design of my circuit board. 

 

The picture below show an example of data pin connected to standard I/O 

 

Thank you in advance for your explanations 

Bel' 

https://www.alteraforum.com/forum/attachment.php?attachmentid=7491
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2 Replies
Altera_Forum
Honored Contributor II
109 Views

DQS is a double-data-rate DDR SDRAM signal. The DE2-115 contains single-data-rate (SDR) SDRAM 

 

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=165&no=502&partno=2 

 

SDR transfers data only on one clock edge and is slower than DDR (which uses both edges). 

 

Before you perform a timing analysis, make sure to add appropriate pin capacitance to the FPGA I/O pins (the flash and SDR SDRAM data sheets will have their pin capacitance values).  

 

If you've never done this before, look at the example design in this thread (its not for SDR SDRAM, but the concepts are similar); 

 

http://www.alteraforum.com/forum/showthread.php?t=41009 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor II
109 Views

Thank you for this explanation. I did not know that the DDR transmits on both edge. :cool:

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