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DE2-115 tPad LCD-TFT 800x600 Display timing

Altera_Forum
Honored Contributor II
1,094 Views

Hello, 

 

I'm fiddling with this development kit, and struggle with understanding the Terasic spec from the tPad User Manual. 

https://www.cl.cam.ac.uk/teaching/1314/ecad+arch/labs/files/tpad_user_manual.pdf 

 

These are the timing specs: 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12816&stc=1  

 

Looks like Terasic used this hardware: 

http://gamma.spb.ru/media/pdf/tft-displei/am-800600gtmqw-00h.pdf 

 

 

Anyhow, I've read up on CRT timing in general and found these excellent descriptions. 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12817&stc=1  

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12818&stc=1  

 

I guess there is no need for VSYNC and HSYNC, as the display accepts DCLK, DE and PIXEL DATA only. 

The terminology used in these diagrams is VBP, rows, VFP, HBP, columns and HFP etc. 

 

My challenge now is understanding the terminology and symbols used in the Terasic LCD-TFT Spec! FDEH, TDEL, FDH++ 

 

Does anyone in this forum know how I can translate/map these? Help would really be appreciated. 

 

 

 

/Stride
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2 Replies
Altera_Forum
Honored Contributor II
119 Views

Solved! 

 

Rudimentary and newbie code, but it does generate position and lcd data enable for when to send pixel color :) 

 

LIBRARY ieee ; USE ieee.std_logic_1164.all ; use ieee.numeric_std.all; ENTITY lcd_driver IS GENERIC ( hres : UNSIGNED (10 downto 0) := "01100100000"; -- 800 hbp : UNSIGNED (10 downto 0) := "00100000000"; -- 256 vres : UNSIGNED (10 downto 0) := "01001011000"; -- 600 vbp : UNSIGNED (10 downto 0) := "00000011100" -- 28 ); PORT ( dclk : IN STD_LOGIC; en : IN STD_LOGIC; de : OUT STD_LOGIC; h_pos : OUT UNSIGNED (10 downto 0); v_pos : OUT UNSIGNED (10 downto 0) ); END lcd_driver ; ARCHITECTURE arch_lcd_driver OF lcd_driver IS SIGNAL v_counter : UNSIGNED (10 downto 0) := "00000000000"; SIGNAL h_counter : UNSIGNED (10 downto 0) := "00000000000"; BEGIN PROCESS (dclk) VARIABLE pv_counter : UNSIGNED (10 downto 0) := "00000000000"; VARIABLE ph_counter : UNSIGNED (10 downto 0) := "00000000000"; BEGIN IF (dclk'EVENT AND dclk = '1') THEN IF (en = '1') THEN ph_counter := ph_counter + 1; IF (ph_counter = hres + hbp) THEN ph_counter := "00000000000"; pv_counter := pv_counter + 1; END IF; IF (pv_counter = vres + vbp) THEN pv_counter := "00000000000"; END IF; ELSE ph_counter := "00000000000"; pv_counter := "00000000000"; END IF; END IF; v_counter <= pv_counter; h_counter <= ph_counter; END PROCESS; de <= '1' WHEN (v_counter < vres AND h_counter < hres) ELSE '0'; v_pos <= v_counter WHEN (v_counter < vres AND h_counter < hres) ELSE "00000000000"; h_pos <= h_counter WHEN (v_counter < vres AND h_counter < hres) ELSE "00000000000"; END arch_lcd_driver ;
Altera_Forum
Honored Contributor II
119 Views

Hi, just at first eye view, I don't see front and back porch timing nor I see sync timing, these are to be respected otherwise LCD panel can be damaged or display in worst mode. 

After that you need also stream out pixel data from memory, if some color translation exist map also color space before to drive display digital lines. 

Regards
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