FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

DE2-70 PAL Video input

Altera_Forum
Honored Contributor II
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Hi everyone, 

the TV Box demo of the DE2-70 board is configured for NTSC video source only. Could you please give me some guideline to modify the source code for PAL video input? I'm very thankful for every hints and it would be nice if you want to provide me some source code. 

 

Thank you very much in advance. 

 

Regards, 

Hanel
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Altera_Forum
Honored Contributor II
289 Views

Check the "Clocked Video Input" component parameters in SOPC builder.

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Altera_Forum
Honored Contributor II
289 Views

Hi, 

I found the solution based on the TV Demo for the DE2-115 DEV Kit, downloaded from the terasic website (DE2_115_v.1.0.5_SystemCD). This demo supports both NTSC and PAL inputs.  

 

Have a nice time!
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Altera_Forum
Honored Contributor II
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Hi, 

 

I also tried to modify the source code based on (DE2_115_v.1.0.5_SystemCD) and also, I modified TD_Detect to match PAL input but seem like it did't success. The result is inspiring but problems still occur. The image produced on the VGA monitor is not stable, it's 'jumping'. I attached my modified code here and it is possible for you to share your code too? Other than that, I had some question about how to obtain the value below? Thanks ! 

 

.WR1_MAX_ADDR(NTSC ? 640*507 : 640*576), // 525-18 

 

.RD1_ADDR(NTSC ? 640*13 : 640*42), // Read odd field and bypess blanking 

.RD1_MAX_ADDR(NTSC ? 640*253 : 640*282), 

 

.RD2_ADDR(NTSC ? 640*267 : 640*330), // Read even field and bypess blanking 

.RD2_MAX_ADDR(NTSC ? 640*507 : 640*570), 

 

Best regards, 

TWK
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