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Altera_Forum
Honored Contributor I
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DE2-70 with D5M Camera

Hey, 

 

I am working with the DE2-70 dev kit and the D5M camera. From my understanding, the demo for the camera uses both sdrams on the kit. I am trying to make it so the camera only uses one sdram. However, I haven't been successful with this thus far... 

 

The things that I have altered are in the Sdram_Control_4Port.v file: 

// Internal Address & Length Control always@(posedge CLK or negedge RESET_N) begin if(!RESET_N) begin rWR1_ADDR <= 0; rWR2_ADDR <= 22'h200000; rRD1_ADDR <= 0; rRD2_ADDR <= 22'h200000; rWR1_MAX_ADDR <= 1280*1024; rWR2_MAX_ADDR <= 22'h200000+1280*1024; rRD1_MAX_ADDR <= 1280*1024; rRD2_MAX_ADDR <= 22'h200000+1280*1024; rWR1_LENGTH <= 256; rWR2_LENGTH <= 256; rRD1_LENGTH <= 256; rRD2_LENGTH <= 256; end  

 

and in the top file: 

 

Sdram_Control_4Port u8 ( // HOST Side .REF_CLK(iCLK_50), .RESET_N(1'b1), .CLK(sdram_ctrl_clk), // FIFO Write Side 1 .WR1_DATA({sCCD_G,sCCD_B}), .WR1(sCCD_DVAL), .WR1_ADDR(0), .WR1_MAX_ADDR(1280*1024), .WR1_LENGTH(9'h100), .WR1_LOAD(!DLY_RST_0), .WR1_CLK(CCD_PIXCLK), // FIFO Read Side 1 .RD1_DATA(Read_DATA2), .RD1(Read), .RD1_ADDR(0), .RD1_MAX_ADDR(1280*1024), .RD1_LENGTH(9'h100), .RD1_LOAD(!DLY_RST_0), .RD1_CLK(VGA_CTRL_CLK), // FIFO Write Side 2 .WR2_DATA({sCCD_G, sCCD_R}), .WR2(sCCD_DVAL), .WR2_ADDR(22'h200000), .WR2_MAX_ADDR(22'h200000+1280*1024), .WR2_LENGTH(9'h100), .WR2_LOAD(!DLY_RST_0), .WR2_CLK(CCD_PIXCLK), // FIFO Read Side 2 .RD2_DATA(Read_DATA1), .RD2(Read), .RD2_ADDR(22'h200000), .RD2_MAX_ADDR(22'h200000+1280*1024), .RD2_LENGTH(9'h100), .RD2_LOAD(!DLY_RST_0), .RD2_CLK(VGA_CTRL_CLK), // SDRAM Side .SA(oDRAM0_A), .BA(oDRAM0_BA), .CS_N(oDRAM0_CS_N), .CKE(oDRAM0_CKE), .RAS_N(oDRAM0_RAS_N), .CAS_N(oDRAM0_CAS_N), .WE_N(oDRAM0_WE_N), .DQ(DRAM_DQ), .DQM({oDRAM0_UDQM1,oDRAM0_LDQM0}) );  

 

When I run it - the vga output is messed up.. I have looked at the older camera demo and they use a single sdram for it - I am not sure what I am doing wrong or haven't done. 

 

Thanks in advance..
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7 Replies
Altera_Forum
Honored Contributor I
52 Views

Hi there, I'm also beginner in Verilog. But looking at your program, the top file output for the sdram is only 16 bits. As I know, the vga code included in the demo needs 30 bits inputs per vga_ctrl_clk. I thing u have to convert the sdram_control_4port to make the output 32 bits. Or you can used the original code.

Altera_Forum
Honored Contributor I
52 Views

You can use 16 bits instead. Pulled this code from ousmu. It should work. 

 

Sdram_Control_4Port u8 ( // HOST Side 

.REF_CLK(iCLK_50_2), 

.RESET_N(1'b1), 

.CLK(sdram_ctrl_clk), 

 

// FIFO Write Side 1 

.WR1_DATA({drRed[11:7], drGreen[11:6], drBlue[11:7]}), 

.WR1(sCCD_DVAL), 

.WR1_ADDR(0), 

.WR1_MAX_ADDR(800*480), 

.WR1_LENGTH(9'h100), 

.WR1_LOAD(!DLY_RST_0), 

.WR1_CLK(CCD_PIXCLK), 

 

// FIFO Read Side 1 

.RD1_DATA(Read_DATA3), 

.RD1(Read), 

.RD1_ADDR(0), 

.RD1_MAX_ADDR(800*480), 

.RD1_LENGTH(9'h100), 

.RD1_LOAD(!DLY_RST_0), 

.RD1_CLK(~ltm_nclk), 

 

// SDRAM Side 

.SA(oDRAM0_A[11:0]), 

.BA(oDRAM0_BA), 

.CS_N(oDRAM0_CS_N), 

.CKE(oDRAM0_CKE), 

.RAS_N(oDRAM0_RAS_N), 

.CAS_N(oDRAM0_CAS_N), 

.WE_N(oDRAM0_WE_N), 

.DQ(DRAM_DQ[15:0]), 

.DQM({oDRAM1_UDQM0,oDRAM0_LDQM0}) 

); 

 

// add by oomusou for RGB16 

assign Read_DATA4 = {Read_DATA3[10:6], Read_DATA3[4:0], 5'h00}; 

assign Read_DATA5 = {Read_DATA3[5:5], 4'h0, Read_DATA3[15:11], 5'h00};
Altera_Forum
Honored Contributor I
52 Views

thanks for the replies... 

 

I would prefer not to drop the image down to 16bit.. I think that the system is capable of coping with the full raw data - however I am pretty new to it all so was hoping that someone would advise on exactly where I was going wrong.. 

 

Again, thanks for the replies..
Altera_Forum
Honored Contributor I
52 Views

Ok then, u do not understand what I mean right. Instead of using 1 sdram in the de2-70 board, the original code is used 2 sdram. If i'm not mistaken, the sdram controller assign as u8 and u9. FYI, the original code is used 2 sdram to be able read and write in 32 bits per cycle. So, if u want to convert the code by only using 1 sdram, u have to create new fifo controller with 30 bits in/out to be able load by vga. The clock for the buffer u create must be twice vga_ctrl_clk. Load 2 times to buffer from sdram then load by vga 1 times. If not, u wont be able to load 30 bits data to vga.

Altera_Forum
Honored Contributor I
52 Views

Hi, 

 

I hope this thread is still being viewed. I have a DE2 board and would like to know why the WR_LENGTH and RD_LENGTH are given the value 256? What is the use of the FIFO length here?
Altera_Forum
Honored Contributor I
52 Views

I've been working on D5M camera module for static image capturing using DE2 (not DE2-70) development board recently. The camera is integrated with nios2 system used for biometric image processing.  

 

I made some changes to the image buffer (default SDRAM) because I needed it for program memory. So, i toss away the SDRAM design in D5M and used onchip memory as image buffer. However, the onchip memory on Cyclone II is too small. I can only capture 100x100 bayern pattern picture. :( 

 

I hope to port this design on larger FPGA, maybe DE3 board with Stratix III.
Altera_Forum
Honored Contributor I
52 Views

Can someone answer this please? I am interested in this question as well.