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Altera_Forum
Honored Contributor I
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DE2 Board External RAM Read/Write Issue

Hello everyone, 

 

My lab partner and I are trying to use the external RAM chip on the DE2 board by building an interface to it in VHDL, following the procedure recommended in Part IV of this lab: 

ftp://ftp.altera.com/up/pub/laboratory_exercises/de2/digital_logic/vhdl/lab8_vhdl.pdf 

 

The problem we are having is that writes to the memory happen at the wrong time. They do not seem to be controlled by the status of the RAM chip's write enable pin; instead, the following happens: 

 

*If I go through the necessary steps to perform a write operation, then flip SW16 (which is not connected to the write enable pin, but serves as an independent signal for my program), then trigger the clock, the value that is on the switches at the moment I trigger the clock gets written to memory -- even if the chip's WE pin is pulled high. Subsequent reads don't trigger a write. 

 

*Changing the address while in read mode, then attempting to read again, triggers a write. This happens even though we don't have an explicit address assignment in the code at this time. 

 

Code appears below. Note the line that is commented out (the one which is setting the bidirectional data bus to high impedance). If that line of code is activated, any attempt to read the memory puts "FF" on the display. (Sometimes the actual value in memory will show for a split second before it is forced to "FF.") We tried setting the data bus to "don't care" or assigning it to itself instead; this didn't force the display to FF, but failed to solve the problems mentioned above. 

 

LIBRARY ieee; USE ieee.std_logic_1164.all; entity part3 is port(SW : in std_logic_vector(17 downto 0); LEDG : out std_logic_vector(8 downto 0); KEY : in std_logic_vector(3 downto 0); HEX0 : out std_logic_vector(6 downto 0); HEX1 : out std_logic_vector(6 downto 0); HEX4 : out std_logic_vector(6 downto 0); HEX5 : out std_logic_vector(6 downto 0); HEX6 : out std_logic_vector(6 downto 0); HEX7 : out std_logic_vector(6 downto 0); SRAM_CE_EN : out std_logic; SRAM_OE_EN : out std_logic; SRAM_WE_EN : out std_logic; SRAM_UB_EN : out std_logic; SRAM_LB_EN : out std_logic; SRAM_ADDR : out std_logic_vector(17 downto 0); SRAM_DQ : inout std_logic_vector(15 downto 0)); end entity part3; architecture behavior of part3 is signal addr : std_logic_vector(17 downto 0); signal clk : std_logic; signal data : std_logic_vector(15 downto 0); signal data_out : std_logic_vector(7 downto 0); signal wren : std_logic; begin clk <= KEY(0); SRAM_CE_EN <= '0'; SRAM_OE_EN <= '0'; SRAM_UB_EN <= '0'; SRAM_LB_EN <= '0'; reg: process (clk) is begin if falling_edge(clk) then addr <= "0000000000000" & SW(15 downto 11); data <= "00000000" & SW(7 downto 0); wren <= SW(16); end if; end process reg; SRAM_WE_EN <= not SW(17); test: process(addr, data, wren) is begin if wren = '1' then SRAM_DQ <= data; data_out <= data(7 downto 0); else data_out <= SRAM_DQ(7 downto 0); --SRAM_DQ <= (others => 'Z'); end if; end process test; --the rest of the code consists of decoders for the seven-segment displays, so that they will display addr, data, and data_out as hex charactersOther notes: 

The "wren" signal and the actual write enable signal are connected to separate switches so that we can pulse the write signal. For the purposes of the program, it was most convenient to have "wren" be a level-sensitive signal; however, the RAM chip's datasheet indicates that it actually stores data on the rising edge of WE. Therefore, we used SW17 for WE, and would switch it on, then off again when attempting to perform a write.
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Altera_Forum
Honored Contributor I
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Finally got the answer -- our pin signals were misnamed. The standard pin names for all those enable signals end in "_N", not "_EN." Once we fixed that, we were able to use the high-impedance assignment without forcing the bus high, and then reading and writing worked properly.