I am using 76MHz clock connected via the ext_clk SMA connector. This clock follows 8bits of digital data via the DE2 JP2 connector. In addition there is additional frame signal that marks when the data is relevant (also connected via the JP2). I would like to know what is the board delay at 25C. I saw the clock passes LVDS driver then connected to the Altera chip. The JP2 passes via resistor and a wire to the Altera. I would like to know the board delay in order to synchronize the 76MHz data. What constrains are required to be added to the project_name.QSF file to support the timing. I can control the delay of the clock and frame signal using external electronics. Thanks in advance, Mic.