FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

DE2 JP1/JP2/GPIO_1 issue

Honored Contributor II

Hi all, 


I am having issues with my Altera DE2 board. I have developed a NIOS II softcore processor with two PIOs. One is an input from SW[7..0] and the other is a 12bit output. During the inital testing phase I wired the outputs to LEDR[11..0], and everything was fine and dandy. Code ran flawlessly. 


Great, now onto the next stage. All I did was change the outputs from LEDR[11..0] to "GPIO_1[26],GPIO_1[24],GPIO_1[22],GPIO_1[20],GPIO_1[18],GPIO_1[16],GPIO_1[14],GPIO_1[10],GPIO_1[8],GPIO_1[6],GPIO_1[4],GPIO_1[2]". I had to only use the even pins because of the way my cables connected to the board. I skiped GPIO_1[10] because it is a ground. I recompile the quartus project, load the sof file onto my DE2, load the .elf file back onto the board. I expect the outputs that I was seeing on LEDR[11..0] to now be on the JP2 pins. Problem is it isn't. I run the code...and random leds on the board start blinking instead. (I see LEDR17, LEDR8, LEDR9, and even some of the 7-segment LEDs). I know the pin assignments are correct because I used the .csv file supplied by Altera. I have no idea what is going wrong. 


Any suggestions/ideas?
0 Kudos
0 Replies