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Altera_Forum
Honored Contributor I
1,323 Views

DE2 SRAM read/write problem

I want make a program that can read/write data with sram on de2 board 

But I has a trouble with read data! This only can read when I remove " this line" in the code! (I test this with de2 controlpanel) when I don't remove "this line" the program only can write!  

 

library ieee; 

use ieee.std_logic_1164.all; 

entity sram is 

port( clock_50:in std_logic; 

sw: in std_logic_vector(17 downto 0);  

ledr: out std_logic_vector(15 downto 0); 

sram_dq: inout std_logic_vector(15 downto 0); 

sram_addr: out std_logic_vector(17 downto 0); 

sram_we_n,sram_oe_n,sram_ub_n,sram_lb_n,sram_ce_n: out std_logic 

); 

end sram; 

 

architecture behavior of sram is 

signal clk,w,r: std_logic; 

signal datain,dataout: std_logic_vector(15 downto 0); 

 

begin 

 

datain<="00000000"&sw(15 downto 8) ; 

sram_addr<="0000000000"&sw(7 downto 0); 

ledr<=dataout; 

sram_ce_n<='0'; 

sram_ub_n<='0'; 

sram_lb_n<='0'; 

 

process (sw(17 downto 16),clock_50) is 

begin 

 

case sw(17 downto 16) is 

 

--read  

when "10" => 

sram_oe_n<='0'; 

dataout<=sram_dq;  

 

--write  

when "01" => 

sram_we_n<='0'; 

sram_dq<=datain;--- this line 

 

when others => 

sram_oe_n<='1'; 

sram_we_n<='1'; 

 

end case; 

 

end process; 

 

end behavior;
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2 Replies
Altera_Forum
Honored Contributor I
52 Views

You forgot to drive sram_dq to three-state when not writing to the RAM. 

sram_dq<= (others=>'Z') should be added to the other cases.
Altera_Forum
Honored Contributor I
52 Views

Thanks alot! The problem is that I don't pay enough attention for clarify interface modes!

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