Hi all !!, my name is Alberto. I'm a very begginer in FPGA's. Most experience in microcontrollers.I'm trying to learn some about this, with the Altera DE2 board. I'm trying to test SDRAM code from the USB-API demo, but...., in asyncronous mode, (like the AS1). The point is: I can't get write or read, at least one byte from memory. Reading the stuff in Sdram_Multiplexer.v, I supposse that I only need to set the "iAS1_WR_n <= 1'b1", write address, and the data, to get one byte saved in memory, but I found that I only get only one hexadecimal digit saved instead all word of "4'hxxxx", also, I noticed that I don't know ...when?? the data was saved in SDRAM....because I've not any "wire" or "reg" that tell me that (feedback from SDRAM in this mode). So is there any place, where to find a functional code about it..or...how to use SDRAM in AS1, AS2, or AS3 ??. (To try to understand it more.) I've tried before using "Host side" part...and I get it work !...but only one byte at time, and with a very slow speed of process. I was reading another SDRAM core that I found in this site, but it is a bit different at the time of manage the data...so I still don't try it. Anyway... DE2 board manual say that I can use the async ports to test my own code, and that is what I want to do. Thank so much all in advance. Alberto.
If you just want to do read and write data to and from SDRAM then you can use SOPC to design a complete system with NIOS II processor and required peripherals, then you can easily access SDRAM through NIOS II IDE by writing simple C code.
The Terasic demonstration examples are a matter apart. They are hopefully operational as such, but they are almost unsuitable to learn about FPGA programming, as they lack any comment or general description.As far as the code is basically functional, it can be understood, but without any comment, it's a bit like reverse engineering, I think. It's probably more fruitful to take an example from a textbook and write the code from the scratch. Really annoying. Some years ago, I implemented a SDRAM controller from an Altera VHDL reference design and it's still used in various applications.
@Ketan.Yes, I "supossed" that it is possible to do, implementing a NIOS II processor, but I began to learn some about FPGA's three weeks ago. Maybe (I think) NIOS II is a quite advanced for me at this momment. Maybe later, now I'm dealing with Verilog programming, and a lot of things more. @FvM. Wow !, from your view point, I choose the poor way to begin with it....and yes, the Terasic code is not commented at all, and is very hard for me to understand somethings. (I thought was my "head"...) So, taking both suggest, maybe I should have more patient, and continue reading and reading a lot of text's. And about the SDRAM code, maybe would be better, to try with the core (that I comment before) downloaded from the Altera forum site (I can't found again that thread to name it here... but I've downloaded it), It is well explained & doccumented. If you want, or need it, to know what I'm talking about, I could upload it in this thread, please let me know. Your both suggests were usefull & I appreciate them, thanks again. Alberto.
If you don't succeed with the Terasic SDRAM core and not need it's special functions, particularly the multi-port option, I would try the other one. May be other users have respective experiences and suggestions, too.
Hi Frank.In fact after your comments, I leave the try with the Terasic code, at least talking about SDRAM. Looking for some threads (questions and answers, of anothers beginners in the forum), I found a thread, where you upload a code in VHDL, with a .pdf for use as explanation refence. And that pdf, results be the same, as I have in the code that I downloaded before and I commented about. Although the code I've is in verilog, and say it was made by "Northwest Logic" in the 2000 year. The thread I named above is: http://www.alteraforum.com/forum/showthread.php?t=2054&page=2&highlight=sdram So now I'll be going for this new try... the pdf is very well explained. I hope to get write and read some bytes in the SDRAM at a relative fast data rate, and learn more and more. Thx && Regards. Alberto.
Hello Alberto,yes, the VHDL code is the Altera reference design I used in my applications. I found some indications, that it may have been ported from Verilog, e. g. there is a comment about an always block. The VHDL design could be implemented rather easily as far as I remember, the only change I applied was to assign a fast output enable register to the datapath OE signal, that would be a bit late otherwise. Good luck, Frank