DE2i-150 | SSRAM Memory | Memory tests Fails

[Altera_Forum]

Hello All, 

 I am trying to do a prototype for my new board on DE2i-150 eval board. Where I would like to run an application from SSRAM memory.   I am trying to use the reference design "DE2i_150_WEB_SERVER_MII1" provided by them along with the CD. [ http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=139&no=529&partno=1 ]  In this reference design, if I run a memory tests on SSRAM, its failing. I tried to access SSRAM memory space from my application [running on SDRAM], I can see an unstable [Reading the same location leads to wrong different data] results from SSRAM memory space.   Is it a configuration issue for SSRAM ? or Do I have to do some changes in board/application [like make FLASH under reset while operating SSRAM - since pins are shared between SSRAM and FLASH] ?   It will be great, If anyone can give some insight for this issue.   Regards Vinod PA

[Altera_Forum]

--- Quote Start ---   It will be great, If anyone can give some insight for this issue.    --- Quote End ---   The most likely problem is a timing issue. You can investigate using several methods;  1. Ensure that the interface has timing constraints   a) The project has an SDC file and that file includes timing constraints for the SSRAM interface.  b) The project compiles with no warning messages from TimeQuest.  c) TimeQuest can be used to view the SSRAM interface signals   If the developers of the examples have "cut" the paths to the SSRAM, then you will not get TimeQuest warnings, but you will also not be able to analyze the SSRAM interface signals in TimeQuest.  2. Review the TimeQuest timing constraints.   Make sure they make sense relative to the data sheet, and that the pin capacitance settings reflect the multiple loads on the shared Flash/SSRAM bus.  3. Change the SSRAM interface to use a clock from a PLL.   Send one PLL output clock to the SSRAM and another to your FPGA I/O registers. Sweep the PLL phase for the clock output used by the FPGA or the SSRAM (but not both at the same time), either by resynthesizing the design, or by using an ALTPLL_RECONFIG component. This will allow you to determine the interfacing timing margin.  Cheers, Dave

[Altera_Forum]

Hello Dave, 

 Thanks for your suggestions.  I couldn't able to find any timing constrains are given for SSRAM interface.   Let me try to use PLL clk for SSRAM module and given some constrains for the interface. I will update you my results asap.   Regards Vinod PA

[Altera_Forum]

--- Quote Start ---   I couldn't able to find any timing constrains are given for SSRAM interface.    --- Quote End ---   That is unfortunate. Poor examples teach bad habits. No example design should be provided without good timing constraints.    --- Quote Start ---   Let me try to use PLL clk for SSRAM module and given some constrains for the interface. I will update you my results asap.    --- Quote End ---   That should be sufficient to get things working.   If you need an example of an .SDC file, I created one for the Altera SDRAM controller in this DE0-nano example ...  http://www.alteraforum.com/forum/showthread.php?t=45927  Cheers, Dave

[Altera_Forum]

Hello Dave, 

 Thanks for sharing the example files with me. I hope that that will be useful for me.  Regards Vinod PA