Dear all,I'm facing an issue when using the DDR2 controller of QSYS on a DE4. When i tried to simulate it through the nios2 interface (after generate testbench), the DDR2 signals (status_local_init_done) seems to never be assert which blocks my design from pursue its execution (I have simulated more that 1ms). The problem also occurs on the FPGA it self. I've looked inside the DDR controller, the PLL and the DLL are locked and calibration is never ending. The controller is actually doing stuff as they are transaction to the external memory signals (which are not mine). Has anyone encountered the same problem before me and do you have a cure for it ? Thank you in advance. Laurent.