FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
6149 Discussions

DE5-Net uses only 4 PCIe lanes

Altera_Forum
Honored Contributor II
1,248 Views

Hi everyone, 

 

after installing a DE5-Net I ran the aocl diagnose acl0 command and I saw that the top transfer speed was of only 1124.51 mb/s and 1559.28 mb/s for writes and reads respectively. 

It looked odd since the beginning because with 8 lanes that transfer at 500MB/s/lane I have a nominal speed of 4000 MB/s and the results I got show only a 38% of efficiency in the driver. 

Thereafter, I wrote my own OpenCL benchmark increasing the block size and I got similar results. Still perplexed, I looked into the driver and I found the following statement: 

 

--- Quote Start ---  

The driver achieves approximately 3100 MB/sec on gen2 x 8 PCIe core with SG DMA on Stratix IV GX FPGA (77.5% efficiency) 

--- Quote End ---  

 

 

This showed me that I'm getting only half of the achievable bandwidth. 

Finally, using the PCI utilities I found out that even if the PCI slot is a x8 the card has negotiated a x4 width (see output below). 

 

Is it a driver problem?  

Am I missing something? 

Does somebody know how to use all the 8 lanes?  

 

p.s: I don't know if it's relevant or not, but I also made sure that PCI Express Control DIP Switch on the bottom is set as suggested in the user manual: SW7.1 and SW7.2 off, and SW7.3 on. 

 

# lspci -vv -s 0a:00.0 

0a:00.0 Unassigned class : Altera Corporation Device ab00 (rev 01) Subsystem: Altera Corporation Device 0004 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 0: Memory at f2100000 (64-bit, prefetchable) Capabilities: MSI: Enable- Count=1/4 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port# 1, Speed 5GT/s, Width x8, ASPM not supported, Exit Latency L0s <4us, L1 <1us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- Capabilities: Vendor Specific Information: ID=a000 Rev=0 Len=044 <?> Kernel driver in use: aclpci
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
570 Views

Ok, I was missing something: BIOS settings :oops: 

 

Mod you can close or delete here. Thanks
0 Kudos
LZERI
Beginner
570 Views

Hello,

 

I have the same problem with Cyclone V SoC kit.

 

Can you tell how you resolved this problem?

 

Best regards

0 Kudos
Reply