DE5a-Net-DDR4 PCIe design

[agula]

Hello,

I am having a strange problem with the DE5a-Net-DDR4 Arria 10 development kit. When I exceed a certain amount of DMA data transfer, the board will all of a sudden lose its bitstream. When the bitstream goes back to the factory default the kernel panics and shuts down. This also makes it impossible to use signal tap since the ILA is no longer set up if the bitstream is lost. Was wondering if anybody knew in what scenarios this could happen. I would appreciate any help. 

Thank you!

[KhaiChein_Y_Intel]

Hi,

Could you check if the below KDBs help?

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/fb365044.html

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd03052014_175.html

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2020/why-does-the-intel--arria--10-pcie--avalon--mm-with-dma-example-.html

Thanks

Best regards,

KhaiY

[agula]

Thank you for these resources, but I do not believe they help. The kernel crashes on the PC because the FPGA is losing its bitstream specifically. I believe the application logic is functioning fine. I am more so curious about why the FPGA is losing its bitstream. I know this may be an issue where I need to contact the manufacturer directly. 

[KhaiChein_Y_Intel]

Hi,

Does this behavior occur consistently? Does the crash happen at a point where a specific DMA transfer start? Could you explain the error in details?

Thanks

Best regards,

KhaiY

[agula]

Hello,

Thanks for the reply. The behavior is very consistent. Whenever I transfer over 2K bytes it seems to crash. The weird thing is that my hardware is receiving all the data correctly and writing it back into  memory correctly. I verified this by printing the DMA memory regions successfully. Even if I transfer more such as 65K bytes, my interrupt generation logic successfully notifies to operating system that all data has been received successfully. Based on this it seems that the application logic is correct. The FPGA loosing its bit stream is whats causing the kernel panic and crash. The only thing I can think of that would cause this is the FPGA is consuming too much power, but this seems unlikely since the designs is not too large.

Thanks   

[KhaiChein_Y_Intel]

Hi,

Could you try to generate an example design and limit to less than 8KB transfer to check if this is design dependent problem?

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best regards,

KhaiY