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Honored Contributor I
924 Views

DEo NANO VCC noise

hi i have a de0 nano and in the gpio headers i am doing pwm at 50MHZ...it have 2 gpio headers of 40 pins .. and i notice that when they are the same ... in the VCC_SYS appear a noise almost 2 Vpp... very big.. 

 

What can i do with that ??? that is normal?
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Honored Contributor I
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Did you connect a load to VCC? Then it may be a problem of missing bypass capacitors. If the pwm signal is driving a large capacitance, e.g. a MOSFET, the ground wire inductance can cause respective ground bounce.

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Honored Contributor I
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i am using pckey CMOS OCTAL BUS BUFFERS(tc74hc541ap)...each PWM FROM THE BOARD IS THE INPUT OF EACH PIN OF THE BUFFERS. the buffer have 10 pF of input capacitence per pin i think. 

 

but when i try to do it without the buffers(just the board, nothing else) the same thing happen.. there was the noise in VCC_SYS...
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Honored Contributor I
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Are you using USB to powering DE0-Nano and how long cable? 

 

When I check schematics there was only 10 uF in VCC_SYS. 

In 3.3V line there was 20 uF and about 16 pcs of 0.1 uF caps. 

 

Do you have measurement pics of noise?
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Honored Contributor I
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Yes i am using an USB cable from about 1.4 m ...to supply the board ... to reduce the noise i have to put a 100 nF capacitor outside the board between ground and Vcc_SYS.. these are 2 pins from one of the GPIO header... and the pics of the noise reduce to 900 Vpp "pic to pic" ... still big .. 

 

 

Do you think that the usb is making noise ? 

 

 

Thankyou!
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Honored Contributor I
24 Views

I don't think, that the problem is generated by insufficient bypassing on the DE0-Nano board. It's most likely in your external circuit and the way how you connect the circuit to the board and how you measure waveforms. In other words, it's about the basics of digital logic design. 

 

Without knowing the exact setup, e.g. cabling, external circuit layout, probe connection, it's difficult to understand the problem details or to give reasonable suggestions.
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