DSP Basic Laboratory Exercise 12 - Intel Community

FPGA, SoC, And CPLD Boards And Kits

FPGA Evaluation and Development Kits

DSP Basic Laboratory Exercise 12

1,136 Views

Hey guys

I am working on this..Not able to get why my code is not working..

I must say I have just begin to do this..no experience at all..

Please let mne know how to approach things..

Link Copied

2 Replies

271 Views

Working on part 1 but not able to get anything from the mic..

put up this code

--YOUR CODE GOES HERE

writedata_left <= readdata_left;

writedata_right <= readdata_right;

read_s <= read_ready;

write_s <= write_ready;

Copy link

271 Views

--YOUR CODE GOES HERE

writedata_left <= readdata_left;

writedata_right <= readdata_right;

read_s <= read_ready;

write_s <= write_ready;

Copy link

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.