FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5927 Discussions

DSP Basic Laboratory Exercise 12

Altera_Forum
Honored Contributor II
1,137 Views

Hey guys 

 

I am working on this..Not able to get why my code is not working.. 

I must say I have just begin to do this..no experience at all.. 

 

Please let mne know how to approach things..
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
272 Views

Working on part 1 but not able to get anything from the mic.. 

put up this code 

 

--YOUR CODE GOES HERE 

writedata_left <= readdata_left; 

writedata_right <= readdata_right; 

read_s <= read_ready; 

write_s <= write_ready;
0 Kudos
Altera_Forum
Honored Contributor II
272 Views

--YOUR CODE GOES HERE 

writedata_left <= readdata_left; 

writedata_right <= readdata_right; 

read_s <= read_ready; 

write_s <= write_ready;
0 Kudos
Reply