Data from FPGA to host

[Altera_Forum]

Hi, 

I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read this (http://www.alteraforum.com/forum/showthread.php?t=32354) and there's instructive information but it's a bit old and maybe there exist other ways. I thought about a FIFO that would be written by the FPGA then read by the host through the USB link. Is it possible? Have I to use a virtual JTAG component? Thanks for your help.

[Altera_Forum]

--- Quote Start ---  But you didn't post any details on the error, just that you had one, so its a bit hard to help :)  --- Quote End ---   Yes I did but it wasn't posted. I had a flashing screen telling why but I didn't have time to read it. Anyway I try another way: sdram_test Writing to 256 SDRAM locations Error:invalid command name "get_service_paths" Error: while executing Error:"unknown_original get_service_paths master" Error: ("eval" body line 1) Error: invoked from within Error:"eval unknown_original $cmd $args" Error: (procedure "::unknown" line 7) Error: invoked from within Error:"get_service_paths master" Error: (procedure "jtag_open" line 9) Error: invoked from within Error:"jtag_open" Error: (procedure "jtag_write" line 7) Error: invoked from within Error:"jtag_write $addr $data" Error: ("uplevel" body line 4) Error: invoked from within Error:"uplevel 1 $cmd" Error: invoked from within Error:"for {set i 0} {$i < $len} {incr i} { Error: set addr Error: set data Error: jtag_write $addr $data Error: }" Error: (procedure "sdram_test" line 4) Error: invoked from within Error:"sdram_test"     --- Quote Start ---   If you're still having trouble, just email me directly (at my forum name).   --- Quote End ---   If you don't mind, I prefer to write on the forum so people can read. I often find solutions to my problems reading forums.

[Altera_Forum]

--- Quote Start ---   If you don't mind, I prefer to write on the forum so people can read. I often find solutions to my problems reading forums.  --- Quote End ---   Great!  The fact that you can an error like "get_service_paths" means you have run the Tcl script in the wrong shell. That script needs to be run from within SystemConsole.  After downloading the design to the DE0-nano, under Quartus II 13.1, you need to select Tools->System Console->System Console, and then once that starts up, you can source the Tcl script that contains the System Console commands, and then the sdram_test will work correctly.  Yes, it would be nice if all Tcl consoles were the same :)  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   After downloading the design to the DE0-nano, under Quartus II 13.1, you need to select Tools->System Console->System Console, and then once that starts up, you can source the Tcl script that contains the System Console commands, and then the sdram_test will work correctly.   --- Quote End ---   When doing that, no other window/console opens.

[Altera_Forum]

--- Quote Start ---  When doing that, no other window/console opens.  --- Quote End ---   Hmm, that's weird.  From the Start Menu, start a NIOS II Command Shell (under the NIOS II EDS folder), and then type system-console in that shell. I just did that on my install and system console started.  If it fails on your setup, then I think you have an installation issue.  Cheers, Dave

[Altera_Forum]

I get "Cannot load library: ***\jvm.dll". 

I'll try to reinstal when I have time.

[Altera_Forum]

--- Quote Start ---  I get "Cannot load library: ***\jvm.dll". I'll try to reinstal when I have time.  --- Quote End ---   Ok, it sounds like you'll need to.  Cheers, Dave

[Altera_Forum]

I get the same error. 

Maybe I should ask my administrator?

[Altera_Forum]

Thanks to this post: http://www.alteraforum.com/forum/showthread.php?t=43498 (http://www.alteraforum.com/forum/showthread.php?t=43498) everything is OK. Let's go on...

[Altera_Forum]

--- Quote Start ---  Let's go on...  --- Quote End ---   Ok, glad to hear you managed to resolve that issue.  Once you have the Qsys design synthesized, you can look at the System Console command script and see how it uses Tcl commands that are described in the Altera documentation. Read that documentation and try to understand the scripts. From that you should be able to see how data can be moved back-and-forth between the FPGA and the PC. Then you can figure out if it meets your needs, eg., the interface might be fast enough to continuously transfer data at the rate you need, or if its not, perhaps you can write a snapshot of data to SDRAM and then transfer that snapshot.  Cheers, Dave

[Altera_Forum]

I was able to run the tutorial entirely and I read the tcl files (I don't know tcl but it is pretty simple to understand) and I don't find all the commands that are used. For example it uses master_read_32 when reading the memory but I can't find what this command is doing. 

Someone told me using an sdram was tricky. Is all the complexity hidden somewhere? Where? How? I think I will use it to store my data and then read it by the host. Is there an easy way to do that?

[Altera_Forum]

--- Quote Start ---  For example it uses master_read_32 when reading the memory but I can't find what this command is doing.  --- Quote End ---    Often, you can use google to answer small questions like this (just plugin the function name to google). See page 10-44 (the 197th page of the PDF) of http://www.altera.com/literature/hb/qts/qts_qii5v3.pdf

[Altera_Forum]

Many thanks. And I see "master_read_to_file" that will be useful to create a file (although it's a binary file and I need to think of that). 

So the system console is able to directly speak with the sdram from simple commands of the user?

[Altera_Forum]

--- Quote Start ---  So the system console is able to directly speak with the sdram from simple commands of the user?  --- Quote End ---    It isn't "direct" as there is a relatively complicated and sophisticated path between your keyboard and the pins on the SDRAM chip, but yes it does allow you to read/write SDRAM data when all the right pieces are in place. And it can do a lot more than that.  Altera offers free training videos and documentation that have introductions to these tools.

[Altera_Forum]

--- Quote Start ---   And I see "master_read_to_file" that will be useful to create a file (although it's a binary file and I need to think of that). So the system console is able to directly speak with the sdram from simple commands of the user?  --- Quote End ---    Look at the block diagram here;  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  (Read the tutorial too!)  Cheers, Dave

[Altera_Forum]

Hi, 

@Dave I started your altera_jtag_to_avalon_mm_tutorial but not finished it yet. For now I have some questions about the de0_nano_sdram tutorial: - Why is there a PLL with two outputs (c0 and c1) at the same frequency? Isn't it possible to use the same clock for qsys design and for the sdram? - Why 100MHz? Couldn't we use the 50MHz oscillator directly? - What need is the synchronizer? The reset couldn't be asynchronous? - There's a sld_hub component in the project. What is it? I can't see this component in the verilog code, why?  And also I wonder why you're not working for Altera but you seem to create good tutorials. You answer many questions on alteraforum. It's really great for beginners (like me), but why? and were do you work? and how do you have so much time to spend for us?  @ted Thanks for the explanation.

[Altera_Forum]

--- Quote Start ---   I started your altera_jtag_to_avalon_mm_tutorial but not finished it yet. For now I have some questions about the de0_nano_sdram tutorial: - Why is there a PLL with two outputs (c0 and c1) at the same frequency? Isn't it possible to use the same clock for qsys design and for the sdram?   --- Quote End ---   There are two 100MHz clocks; one goes to the FPGA logic, the other goes to the SDRAM device (its an output clock).  If you use one clock, the timing analysis of the SDRAM interface would show that it fails timing. By using two clocks, it is possible to meet timing by adjusting the phase of the clock that goes to the SDRAM. Take a look at TimeQuest once the design is synthesized, and then modify it so that the SDRAM clock inside the design is driven from c0 instead of c1.    --- Quote Start ---   - Why 100MHz? Couldn't we use the 50MHz oscillator directly?   --- Quote End ---   50MHz would have been too easy :)    --- Quote Start ---   - What need is the synchronizer? The reset couldn't be asynchronous?   --- Quote End ---   The Quartus handbook has a discussion on why you should use a reset that asserts asynchronously, yet deasserts synchronously. Cliff Cummings also has some nice documents on resets (Google his name).    --- Quote Start ---   - There's a sld_hub component in the project. What is it? I can't see this component in the verilog code, why?   --- Quote End ---   When you add a JTAG-to-Avalon-MM bridge or a component like SignalTap II an SLD HUB is added to the system.    --- Quote Start ---   And also I wonder why you're not working for Altera but you seem to create good tutorials. You answer many questions on alteraforum. It's really great for beginners (like me), but why? and were do you work? and how do you have so much time to spend for us?   --- Quote End ---   I work for a university, but live in the middle of nowhere. Take a look at these slide presentations (the first few links);  https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html  I write the tutorials when I am learning how to use the components myself. I figure if I had trouble understanding Altera's documentation, then others will too, so I post the tutorials to help.  When do I get time to write to the forum? When I'm drinking my coffee ... I guess I drink way to much coffee ... :)  Cheers, Dave

[Altera_Forum]

OK for the PLL, the reset (I'm reading a paper from Cliff Cummings) and the SLD_hub. 

 Today's questions: A user can send commands in the system console but I don't know if I can type at a rate of 1kHz! Can the design put values in the sdram by itself (maybe using a NIOS)? What need is the quartus_stp? What difference with the system_console?   --- Quote Start ---   I work for a university  --- Quote End ---   Are you a professor or what is your work?   --- Quote Start ---   When do I get time to write to the forum? When I'm drinking my coffee ... I guess I drink way to much coffee ... :)  --- Quote End ---   LOL

[Altera_Forum]

--- Quote Start ---   A user can send commands in the system console but I don't know if I can type at a rate of 1kHz! Can the design put values in the sdram by itself (maybe using a NIOS)? What need is the quartus_stp? What difference with the system_console?   --- Quote End ---   You can write a Tcl script that can transfer the data. The "fastest" Tcl method is master_read_memory or master_write_memory. The fastest it can go is about 600kB/s.  You can transfer your data by either writing to one side of a FIFO and reading it via Tcl from the other, or perhaps a slightly easier solution to understand would be to capture a block of samples, and then read them out over Tcl, and then repeat that sequence. The JTAG-to-Avalon-MM tutorial describes how to simulate a Qsys system, so you can always try that too.    --- Quote Start ---   Are you a professor or what is your work?   --- Quote End ---   I'm an engineer building FPGA-based hardware and high-speed ADC interface logic for radio astronomy signal processing. The slides I linked to show what I build.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  or perhaps a slightly easier solution to understand would be to capture a block of samples, and then read them out over Tcl, and then repeat that sequence.  --- Quote End ---   Maybe it seems easier for you but I don't understand this. What does it imply? How does it work?

[Altera_Forum]

--- Quote Start ---  Maybe it seems easier for you but I don't understand this. What does it imply? How does it work?  --- Quote End ---   Have you ever used SignalTap II? If not, go and try to use it. Capture a trace of the signal you are interested in, and then visually look at the traces.  SignalTap II is "just code" and you can duplicate its capture functionality, but rather than displaying the data, you transfer it over JTAG and then analyze the data.  Cheers, Dave

[Altera_Forum]

Sorry I was away for the work. 

Now I'm back on this project. I instantiated a fifo, I've got a qsys system with a Nios II cpu. This system has access to the fifo but I'm lost: has the JTAG to Avalon master bridge you use to be implemented? The signals from the fifo have to go to the sdram controller or to the cpu? The commands you use (as jtag_read or jtag_write) can be used by the cpu or only in the console?