Data from FPGA to host

[Altera_Forum]

Hi, 

I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read this (http://www.alteraforum.com/forum/showthread.php?t=32354) and there's instructive information but it's a bit old and maybe there exist other ways. I thought about a FIFO that would be written by the FPGA then read by the host through the USB link. Is it possible? Have I to use a virtual JTAG component? Thanks for your help.

[Altera_Forum]

Now I still have problems configuring SignalTap II: 

as stated in posts# 54 to# 57 I can't see the "first" edge of the trigger, even when waiting for a long time after starting the acquisition and before starting the process. Surely my configuration is bad but I can't find the problem.

[Altera_Forum]

--- Quote Start ---  Now I still have problems configuring SignalTap II: as stated in posts# 54 to# 57 I can't see the "first" edge of the trigger, even when waiting for a long time after starting the acquisition and before starting the process. Surely my configuration is bad but I can't find the problem.  --- Quote End ---   Try a different solution then.  For example. Rather than trigger off your asynchronous signal, trigger off a counter inside the FPGA. Have that counter enabled by your external signal, but first make sure that external signal is synchronized to the clock used by SignalTap II and the counter. Then trigger off the counter, eg., a count of 1.  Doing this may make you realize what you were doing wrong earlier.  Cheers, Dave