FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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De0 University Board - SD-Ram

Honored Contributor II


I'm using the De0 evaluation board (Terrasic). My target is to build the SD Ram interface (without SOPC). According to manufacter's data sheet (Zentel - A3V64S40ETP), there are 12 address bits. But in De0_user_manual I see that it should be 13 address bits between the FPGA to the SD ram (Have to use it to make the Pin Planning). 

I have downloaded the latest versions of data sheet (both of manufacters) but there is no change.  

Data sheet of the SD Ram that was included in Evaluation Board Pack absolutely unfitted to the SD ram chip located on the Board De0. 

I'll be glad to listen to every idea. 

Thanks a lot
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