FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

De0-nano jtag I/O standard

Altera_Forum
Honored Contributor II
1,011 Views

Hi everybody 

 

I was doing a simple nios2 tutorial whit my de0-nano board while I noticed one thing. After synthesis I can find, in the pin planner, the reserved pins for the JTAG interface and the I/O interface for those pins is set to 2.5 V as default (for the other pins I use 3.3 LVTTL as required on the de0-nano manual). According to the Cyclone IV datasheet the JTAG pins are part of the I/O bank 1 so the VCCIO1 is the operating voltage for that bank. 

In the de0-nano board, according to the manual, the VCCIO pin for all the banks are connected to the 3.3 V rail. 

 

Now my question which I/O standard must be used? 

If I use 2.5 V can I damage my board or simply it doesn't matter cause the I/O bank is connected to 3.3 V so the standard will be 3.3? 

 

Thanks a lot
0 Kudos
0 Replies
Reply