FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

De10-Nano GHRD UNSTABLE

hsyn
Beginner
768 Views

Hello,

I created a new design with DE10_NANO_SoC_GHRD sample project. There are 2 new ip-cores which are made by me (bw_flash_loader and bw_flash_loader_pin_router) in new design.

The bw_flash_loader have 2 protocols that name are spi and jtag for use to program an ic.

The bw_flash_loader_pin_router is routing signals between ip-cores and gpios.

The bw_flash_loader_subsystem have 2 DMA(for data transfer between hps and fpga ocram), fpga_ocram and bw_flash_loader.

Problem:
When I add 1 or 2 bw_flash_loader_subsystem to design, it works well. But, if I add one more, it is not working stable. When I compile design all time, it works differently. I didn't change any settings or files. I can't understand why works differently all time.
For example;
ipcore-1 works well and ipcore-2 don't work well. I compile design again. ipcore-2 works well and ipcore-1 don't work well.

Lots of DMA are connected to a f2h_axi_slave bus.(multiple_master.png) Is it a problem?


Details:
Optimization mode: Balanced (Default)
clk: 50mhz
Reports folder: All reports are in this folder.
qsf file: DE10_NANO_SoC_GHRD.qsf
sdc file: DE10_NANO_SOC_GHRD.sdc

0 Kudos
4 Replies
EBERLAZARE_I_Intel
453 Views

Hi,

 

The causes may vary, since you have changes in the GHRD which is connected to the HPS, you need to recompile all the design.

E.g recompile in the Platform designer and Quartus, then recompile the device tree, preloader and Uboot.

hsyn
Beginner
438 Views

Hi,

I recompiled all design again but nothing changed. It worked unstable.

I didn't add any constraint for spi and jtag pins. 

Which subject should I focuse to? Platform Designer(connections and parameters) , timing constraints , Assignment Editor Parameters (current strength, slew rate, etc.) , own ip cores or verilog codes , noise and reflections , etc.

hsyn
Beginner
402 Views

if there is a problem about timing constraints, in this case, it does not work stable with high spi frequencies, does it? But, it didn't work well(not stable) with low spi frequencies also.

EBERLAZARE_I_Intel
335 Views

Hi,

It seems that this might be a timing issue after adding those components mentioned.

You need to properly constrain your design.

Reply