De2-115 windows application to control Cyclone chip

[Altera_Forum]

Hi, 

I bought Altera board (development) DE2-115 In the example CD - there is a very nice PC application with UI - when pressing buttons-> altera board light leds, show LCD when you write in PC etc. I would like to develop myself FORM (C sharp or visual C) that will control my board (at first light leds by the button I am pressing for example)  Unfortunately there are no any sources, furthermore I contact terasic (board manufacture) and they don't give any code or sources.  After some searches I have found that Altera board uses USB chip of Cypress which uses FTDI driver.  So now I know I need: 1. write PC code - that uses FTDI DLL to transfer data to board. 2. The FTDI DLL 3. Altera code to identify commands  Now the only example is with Verilog, and NIOS II - SOCP, and Eclipse. But I would like to read the chip JTAG inputs with some VHDL code  Is any one familiar how to start doing this, or have any example (VHDL is preferred)? Any help will help  Thanks, Roee

[Altera_Forum]

The official (and documented) way to do this is to use system console. Using SOPC builder or QSys you can create an FPGA system with a JTAG to Avalon master (you don't need a Nios CPU to do that) and in system console you can create a GUI to control your board. System console uses TCL though, and not C# or C++.

[Altera_Forum]

Thank you, 

Can I do this without SOCP builder? - do I have any interuction with the JTAG (internal Jtag of altera)?, Also I would like to do so with VHDL, is this possible without SOCP builder? Does any one have any source file (VHDL) eaxmple that I can use for this? Also if I use UART command, isn't it possible to transfer data to DLL (I guess FTDI DLL) through Visual C or C sharp? Thanks, Roee

[Altera_Forum]

Everything is possible, but using JTAG directly isn't documented so you are on your own and must reverse engineer a lot. I really think learning to use SOPC Builder / QSys and system console would me a more productive use of your time ;) 

You can find a tutorial here: http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial (thanks Dave for reminding me about this tutorial in another thread!) For very simple tests (LEDs, buttons) you just need to use PIO components. For more complex interfaces or modules, you can write your own VHDL code and integrate it as a custom component in your SOPC design.

[Altera_Forum]

--- Quote Start ---  Everything is possible, but using JTAG directly isn't documented so you are on your own and must reverse engineer a lot.   --- Quote End ---   Altera has documented their SLD Virtual JTAG component;  http://www.altera.com/literature/ug/ug_virtualjtag.pdf‎  and I have documented how to use it in detail here:  http://www.ovro.caltech.edu/~dwh/correlator/pdf/vjtag.pdf    --- Quote Start ---   I really think learning to use SOPC Builder / QSys and system console would me a more productive use of your time ;)   --- Quote End ---   I agree. The protocol used by the Avalon-MM bridge is documented here:  http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.zip  You can use that information along with the USB-Blaster protocol  http://sourceforge.net/apps/mediawiki/urjtag/index.php?title=cable_altera_usb-blaster  To access the FTDI device directly and send JTAG-to-Avalon-MM bytes directly. However, you can also do the same thing using Tcl scripts.    --- Quote Start ---   You can find a tutorial here: http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial (thanks Dave for reminding me about this tutorial in another thread!)   --- Quote End ---   This is also a good reference :)    --- Quote Start ---   For very simple tests (LEDs, buttons) you just need to use PIO components. For more complex interfaces or modules, you can write your own VHDL code and integrate it as a custom component in your SOPC design.  --- Quote End ---    Start with the Qsys tutorial and use System Console. Use the Tcl server that comes with that code and access it via C# or whatever language you like.  Cheers, Dave

[Altera_Forum]

Hi Guys, 

Something I misunderstand, If I am using JTAG debugger (in Programmer), I can move bits to JTAG and make CLOCKS and see TDO as I expect, But when I see TDO=1 => I don't see my green led on board lighting? why is that am I missing something? Attached my design Thanks, Roee

[Altera_Forum]

--- Quote Start ---   Something I misunderstand, If I am using JTAG debugger (in Programmer), I can move bits to JTAG and make CLOCKS and see TDO as I expect, But when I see TDO=1 => I don't see my green led on board lighting? why is that am I missing something?   --- Quote End ---   It does not work because you have not read any of the documentation and understood how the JTAG component works.  The TDO from the SLD_Virtual_JTAG component is *NOT* the same as the external pin. There is multiplexing logic in the SLD_Virtual_JTAG component. You need to issue JTAG commands to select your component first. The vjtag.pdf document contains example Tcl code and SignalTap II logic analyzer traces. Add a SignalTap II instance to your design and you will see that TDO will not change until you issue the correct commands.  Cheers, Dave

[Altera_Forum]

Hi Dave 

I have read part of it :) I see there is an instruction set, and seen your example I did do same module as you (I guess this is 6 instructions ?) - of 3 bits I didn't understand yet how to define them Also didn't actually succeed to load the TCL tools to read and write to JTAG, Can you refer me to tools that will work on windows 8 machine? Do I need to install TCL environment to run the TCL tools? keep trying (probably will take me few days) ... Thanks, Roee

[Altera_Forum]

--- Quote Start ---   I have read part of it :)   --- Quote End ---   There is a lot of information in the references I provided. You will have to read all of it, several times.    --- Quote Start ---   Also didn't actually succeed to load the TCL tools to read and write to JTAG, Can you refer me to tools that will work on windows 8 machine? Do I need to install TCL environment to run the TCL tools?   --- Quote End ---   The documentation tells you everything you need to know.   The quartus_stp and SystemConsole tools must be used to accessing JTAG directly - a general Tcl tool does not have support for Altera JTAG access.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

While reading your PDF, I have more question: When you write: "The Virtual instruction register bus from the Virtual JTAG component was connected to GPIO bits and to the LEDs (so that Tcl commands can change the LED state)." This means that I have manually to connect the Virtual Jtag myself to LEDS ? I guess you mean ir_out[2..0] ? So I should connect it manually myself? Also I did not understand how to change Directions - meaning the TDI generally is output of Altera, and just in JTAG mode turns to input? so how should I turn it to input? Also in the timing diagram you mark TDI-ERROR (what would you expect there?) When it is in JTAG mode - by TCL commands, this block get automatically clocks and data? (so I don't have to take care about toggling these pins correct?) So if I have connected my leds correct and gave TCL commands I should see the leds lighting by my input to ir_in[2..0]? When I connect in my block the ir_out[2..0] to LEDS on board I get an error "missing source signal" like this is input why? how can I overcome this problem? Thanks for your help, When my blocks are ready I will share them to all here Thanks, Roee

[Altera_Forum]

--- Quote Start ---   While reading your PDF, I have more question: When you write: "The Virtual instruction register bus from the Virtual JTAG component was connected to GPIO bits and to the LEDs (so that Tcl commands can change the LED state)." This means that I have manually to connect the Virtual Jtag myself to LEDS ? I guess you mean ir_out[2..0] ?   --- Quote End ---   Yeah. Instantiate an SLD_Virtual_JTAG component and a SignalTap II instance. Probe the ir_out[] bus and you'll see that it captures your custom instruction LSBs.    --- Quote Start ---   Also I did not understand how to change Directions - meaning the TDI generally is output of Altera, and just in JTAG mode turns to input? so how should I turn it to input? Also in the timing diagram you mark TDI-ERROR (what would you expect there?) When it is in JTAG mode - by TCL commands, this block get automatically clocks and data? (so I don't have to take care about toggling these pins correct?) So if I have connected my leds correct and gave TCL commands I should see the leds lighting by my input to ir_in[2..0]? Thanks for your help, When my blocks are ready I will share them to all here   --- Quote End ---   I'll dig up my example code and post it. It'll be much easier for you to use a working example.  Cheers, Dave

[Altera_Forum]

Hi, 

Thanks for your help Dave, I just need example of Archived project (.qar file) with lighting LED for every JTAG instruction. From this point I think I will manage (hopefully)  BR, Roee

[Altera_Forum]

Hi Roee, 

 Here's an example I had for the DE2 board. This is not the same board as you have, so you'll have to create your own top-level version of the design. To start with, synthesize the design so you can see how the project is created and the scripts are used. Here's the contents of the readme.txt   Altera SLD_Virtual_JTAG Example Design -------------------------------------- 4/12/2014 D. W. Hawkins (dwh@ovro.caltech.edu) This example design shows how to connect the SLD_Virtual_JTAG component to the LEDs and push buttons on the DE2 board. The Tcl script scripts/vjtag_cmds.tcl can be used from the command-line application quartus_stp to access the GPIO. --------------------------------------------------------------------- Synthesis Instructions ---------------------- 1. Unzip the example source, eg., into C:\temp\de2_sld_vjtag_to_gpio 2. Start Quartus 3. Select the Tcl console (if its not visible, select View->Utility Windows->Tcl Console) 4. Change directory to the top-level of the source tcl> cd {C:\temp\de2_sld_vjtag_to_gpio} 5. Source the synthesis Tcl script tcl> source scripts/synth.tcl The console will output the following messages ... Synthesizing the DE2 'sld_vjtag_to_gpio' design ----------------------------------------------- - Quartus Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition - Creating the Quartus work directory * C:/temp/de2_sld_vjtag_to_gpio/qwork - Changing to the Quartus work directory * C:/temp/de2_sld_vjtag_to_gpio/qwork - Creating the Quartus project * create a new de2 project - Creating the design files list - Applying constraints - Processing the design - Processing completed 6. You can now use the JTAG programmer to download your DE2. If your target board is not the DE2, then you will have to create your own top-level VHDL design and corresponding pin assignments (see constraints.tcl for an example). --------------------------------------------------------------------- GPIO Control Instructions ------------------------- 1. Download the DE2 board 2. Start a NIOS II IDE Shell (Cygwin console) eg. Under Windows XP Start->All Programs->Altera->NIOS II EDS 12.1sp1->NIOS II 12.1sp1 Command Shell 3. View the JTAG nodes $ jtagconfig -n 1) USB-Blaster 020B40DD EP2C35 Node 00406E00 (110:8)# 0 Design hash D1C56CB2D6FF7B6F3030 4. Start quartus_stp $ quartus_stp -s This starts the Tcl interface. 5. Change to the project folder tcl> cd {C:\temp\de2_sld_vjtag_to_gpio} 6. Source the VJTAG Tcl commands tcl> source scripts/vjtag_cmds.tcl 7. Issue VJTAG IR Tcl commands a) Read the JTAG device IDCODE tcl> read_idcode 0x020B40DD b) Read the JTAG device USERCODE tcl> read_usercode 0xDEADBEEF c) Print the Altera Virtual JTAG hub info tcl> print_hub_info Hub info: 0x08086E04 VIR m-width: 4 Manufacturer ID: 0x6E Number of nodes: 1 IP Version: 1 d) Change the VJTAG IR value tcl> jtag_vir 0x1234 38565 The DE2 board red and green LEDs and one of the hex displays will illuminate SLD_IR_WIDTH LEDs, where SLD_IR_WIDTH is the top-level generic on the DE2.vhd design (nominally set to 18-bits). The jtag_vir instruction returns the status of the 18-bits of switches. The value can be converted to hex to make it easier to determine which pins were asserted, eg., tcl> set sw tcl> puts 0x96A5 which matches the settings used during this test. 8. Issue VJTAG DR Tcl commands tcl> jtag_vdr 0x1234 0x55 A SignalTap II trace will show the data serialized on TDI. TDO is configured to toggle, so it will always read 0x55 or 0xAA.    Enjoy!  Cheers, Dave

[Altera_Forum]

Thanks! 

I am using DE2-115 board, so the cyclone II doesn't match I have changed the Device to my device - should I make any more changes? (I guess the TCL that configure pins is not the same) correct? So I will have to use my own TCL for pin configuration. Also seen you configure many things - I guess I don't need so many correct? if just changing Altera to mine I get garbage on LCD Thanks, Roee

[Altera_Forum]

--- Quote Start ---   I am using DE2-115 board, so the cyclone II doesn't match   --- Quote End ---   I know, that is why I warned you NOT to use it directly.    --- Quote Start ---   I have changed the Device to my device - should I make any more changes? (I guess the TCL that configure pins is not the same) correct?   --- Quote End ---   Of course, you have to change the pin assignments. That is clearly stated in the readme.txt. Did you not read it?     --- Quote Start ---   Also seen you configure many things - I guess I don't need so many correct?   --- Quote End ---   This question is not clear.     --- Quote Start ---   if just changing Altera to mine I get garbage on LCD   --- Quote End ---   If you downloaded the design without changing the pin assignments, you may also have damaged your board.  Cheers, Dave

[Altera_Forum]

Is it really possible to damage this boards with wrong configuration? 

If you have signals contention, and the board designer was experienced so you shouldn't worry about board damage :) This is like saying - if you use your PC computer with wrong SW you can burn your PC, I hope this is not possible in this board  I have TCL file of the DE2-115, I have used your script, but change the "proc get_pin_constraints {arg} {" to my board, I guess this is not enough - because the pins name might be different in the VHDL code you used - is this correct?  I have attached the updated TCL for DE2-115 Thanks, Roee

[Altera_Forum]

--- Quote Start ---  Is it really possible to damage this boards with wrong configuration?   --- Quote End ---   It is ABSOLUTELY possible.    --- Quote Start ---   If you have signals contention, and the board designer was experienced so you shouldn't worry about board damage :)   --- Quote End ---   These boards are "evaluation" boards. The designers assume you know how to read a schematic, and will not do anything to damage the I/O.    --- Quote Start ---   This is like saying - if you use your PC computer with wrong SW you can burn your PC, I hope this is not possible in this board   --- Quote End ---   There is very little protection on these boards. If you create a driver conflict, or use an invalid logic level (5V on a 3.3V pin) you will damage the board.    --- Quote Start ---   I have TCL file of the DE2-115, I have used your script, but change the "proc get_pin_constraints {arg} {" to my board, I guess this is not enough - because the pins name might be different in the VHDL code you used - is this correct?   --- Quote End ---   That is right. You have to have matching pin assignment constraints and top-level HDL pin names. Review the .pin file generated by Quartus until things match.    --- Quote Start ---   I have attached the updated TCL for DE2-115   --- Quote End ---   You're on the right track. Now you have to make sure your top-level HDL names match and check the .pin file.  Cheers, Dave

[Altera_Forum]

Hi, 

when you say   --- Quote Start ---   You have to have matching pin assignment constraints and top-level HDL pin names. Review the .pin file generated by Quartus until things match.   You're on the right track. Now you have to make sure your top-level HDL names match and check the .pin file.   --- Quote End ---    Just to clarify that I have understood: When I changed the "constrains.tcl" pin assignment -> I already declared the DE2-115 pin out, so now I have to use these names in project TOP LEVEL.  The TOP LEVEL is DE2.VHD (vhdl file) and not HDL? - is this correct (I don't see any HDL file in project directory)  So what file hold the connection between the Altera chip and TOP level?  The .PIN file is same like going in menu to Assigments -> pins correct? Thanks, Roee

[Altera_Forum]

--- Quote Start ---   The TOP LEVEL is DE2.VHD (vhdl file) and not HDL? - is this correct (I don't see any HDL file in project directory)   --- Quote End ---   HDL just means hardware description language. In my design I used de2.vhd as the top-level HDL file. You could just as easily use a .BDF file.    --- Quote Start ---   When I changed the "constrains.tcl" pin assignment -> I already declared the DE2-115 pin out   --- Quote End ---   Editing the file is not enough. You have to 'source' the file via the Tcl console to change your project settings.    --- Quote Start ---   So what file hold the connection between the Altera chip and TOP level?   --- Quote End ---   You tell Quartus what your top-level design file is. The pin names on the top-level, along with the matching pin assignments defines the top-level pins at the FPGA level.    --- Quote Start ---   The .PIN file is same like going in menu to Assigments -> pins correct?   --- Quote End ---   No. The .pin file is generated during synthesis. Look at the report files.  Cheers, Dave

[Altera_Forum]

Hi 

Again please lets take an example. in DE2.VHD top, I just need to connect all port. e.g. I have:  port (  -- Input clocks  clk_50MHz : in std_logic;  clk_27MHz : in std_logic;  clk_sma : in std_logic;   -- SDRAM  sdram_clk : out std_logic;  sdram_cke : out std_logic;  sdram_csN : out std_logic;  sdram_rasN : out std_logic;  sdram_casN : out std_logic;  sdram_weN : out std_logic;  sdram_ba : out std_logic_vector( 1 downto 0);  sdram_addr : out std_logic_vector(11 downto 0);  sdram_dqm : out std_logic_vector( 1 downto 0);  sdram_dq : inout std_logic_vector(15 downto 0);  etc.  So I need to see that in my constrains file I have same names. And if not -> should fix it in DE2.VHD file  lets take from DE2.VHD more example, I have in file port: -- LCD  lcd_on : out std_logic;  now in constrains.tcl I have line with:  set_location_assignment PIN_L5 -to LCD_ON  ;# LCD Back Light ON/OFF (not working)  so since they both LCD_ON (except capital letters, does it matter?)  => so this is all good, and this port doesn't need any change at all. Right?  Thanks, Roee

[Altera_Forum]

--- Quote Start ---   so since they both LCD_ON (except capital letters, does it matter?)   --- Quote End ---   VHDL is case-insensitive, so it does not matter.  Quartus will answer these questions for you - synthesize the design and read the warning messages. Look at the messages related to missing assignments. Then look at the .pin file and manually check every single pin.  The key to using a top-level file like de2.vhd is that you only have to write the top-level file and constraints *ONCE*, and then carefully check the assignments. For future designs, you use the same top-level design as a template, and you know that the port names and pin assignments are all correct (since you checked them carefully for the first design).  Cheers, Dave