De2-115 windows application to control Cyclone chip

[Altera_Forum]

Hi, 

I bought Altera board (development) DE2-115 In the example CD - there is a very nice PC application with UI - when pressing buttons-> altera board light leds, show LCD when you write in PC etc. I would like to develop myself FORM (C sharp or visual C) that will control my board (at first light leds by the button I am pressing for example)  Unfortunately there are no any sources, furthermore I contact terasic (board manufacture) and they don't give any code or sources.  After some searches I have found that Altera board uses USB chip of Cypress which uses FTDI driver.  So now I know I need: 1. write PC code - that uses FTDI DLL to transfer data to board. 2. The FTDI DLL 3. Altera code to identify commands  Now the only example is with Verilog, and NIOS II - SOCP, and Eclipse. But I would like to read the chip JTAG inputs with some VHDL code  Is any one familiar how to start doing this, or have any example (VHDL is preferred)? Any help will help  Thanks, Roee

[Altera_Forum]

Thanks Dave 

Now I shure have some work to do Just wonder what is the purpose of 7 segments in your code? What is displayed in it ? Also about Tcl commands to Jtag via nios commands, can't I use quartus command shell for it instead the Nios Tool? All the best Roee

[Altera_Forum]

Hi all, 

Thanks to Dave I have made a big progress with this project I can now see JTAG is working and send commands - working!!! I just did adjustment to DE2-115 board (which altera chip is CYCLONE IV E) since the main chip and pins are totally different. Also major changes with components on board (e.g. VGA is now only 8 bits, instead of 10 bits on older board, memory sizes are bigger, and Ethernet controller is different, and many more changes) - almost done with changes  Just wonder if I enter CYGWIN and do all process after command:    tcl> jtag_vir 0x1234 can't send the command:    tcl> jtag_vir 0x1111  like Jtag is closed and need all process from beginning ... Also I could not implement all commands to TCL together, because when entering  $ quartus_stp -s  commands afterwards are not seen attached example file that doesn't work  Thanks, Roee

[Altera_Forum]

Hi Roee, 

 Apologies, when I copied and pasted the instructions into the readme.txt, I forgot to copy the fact that you first needed to open the JTAG connection via 'jtag_open'.  However, had you read the Tcl script, you might have figured that one out yourself :)  Cheers, Dave

[Altera_Forum]

Hi Dave, 

Here is my very basic knowledge at this points about Jtag,  Please see if I am writing something wrong:  1. Jtag- is an interface, was invented in order to enable boundary (chip cells output) - scan, for debug, for reading data out, and for enabling data in 2. The basic concept is that data moves like in shift register, using shift register, that enable to "move data" in and out 3. There is an option to connect many chips in serial and move data between them (I think up to 128 chips), but I mind about 1 only :) 4. The basic JTAG signal (control the Jtag) are generally only 4 (sometime 5) - which are: CLK, TDI, TDO, TMS 5. if we enter JTAG mode, than the chip enter into JTAG mode, and not working like Usual (since we have a mux that enable at this stage data in or data out) 6. Basically to enter JTAG command -> use just CLK and TMS (of corse need the IR and DR registers data also) 7. The Jtag has only 2 registers: IR - for Instructions, DR - for DATA (that is all!) 8. The Length of IR - determine the Max commands we might have (e.g. 3 bits IR - is only 8 commands) 9. The DR is enabling the DATA in/out  This is very basic to start working Is something that is written wrong here? Thanks, Roee

[Altera_Forum]

--- Quote Start ---   Here is my very basic knowledge at this points about Jtag,    --- Quote End ---   JTAG is simply a synchronous serial interface, i.e., it has a clock, data in, data out, and a mode/select bit. Its no more difficult to understand than SPI. However, unlike SPI, there is a standard 'state machine' called the TAP (test access port), which includes instruction and data registers, which you load and read to perform JTAG transactions.  Altera has layered their Virtual JTAG Interface on top of JTAG. The Virtual JTAG interface is implemented in the fabric of the FPGA. Altera define a couple of JTAG instructions for manipulating their Virtual Instruction register and Virtual Data register. This is all explained in this document:  http://www.ovro.caltech.edu/~dwh/correlator/pdf/vjtag.pdf  If this seems overly complicated, you could always just connect a UART to pins on the DE2-115 and write a serial port application. FTDI make several cables that I use;  http://www.digikey.com/product-detail/en/c232hm-ddhsl-0/768-1106-nd/2714139 http://www.digikey.com/product-detail/en/c232hd-ddhsp-0/768-1011-nd/2767783  Cheers, Dave