Debugging DE10-lite with external 10 Pin Blster

[ASidd16]

Hello Everyone,

I want to debug DE10-lite with extenal JTAG header but it only shows MAX II(EPM240) device when i scan it for downloading a file.

Can anyone please guide me what is the problem and how can i approach to my MAX 10 FPGA  except MAX II CPLD.

In schematic the external JTAG header connector is connected to MAX II EPM240 then it's connected to MAX10 FPGA JTAG pins.

The data sheet and schematics:

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=1021&PartNo=4

Thank you very much

[Esteban_D_Intel]

Hello ASidd16,

Thank you for posting on the Intel® communities.

Based on your product MAX 10 FPGA, we would like to inform you that we have a forum for those specific issues and products, so we are moving it to the appropriate support so you can get answered more quickly.

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/bd-p/fpga-soc-cpld-boards-kits

Best regards,

Esteban D. 

Intel Technical Support Technician

[AR_A_Intel]

Hello

Welcome to INTEL forum. The DE10-Lite Board belong to Terasic. It would be better if you could contact Terasic for enquiry related to Terasic board or connection issue. https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=12&No=20

[AR_A_Intel]

We do not receive any response from you to the previous reply that we have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you