Decoupling Cap for 10M16DAF484I7G

[Kang1]

Is there a guideline regarding how to design decoupling cap for 10M16DAF484I7G, it looks like Power Distribution Network (PDN) Design Tool can do the job, but this tool looks like is too complicated for me. It would be good you guys can provide an example for how to do so.

[Maria_R_Intel]

Hello Kang1,

To better assist you, we will move this thread to the proper sub-forum. Please expect a response soon.

Best regards,

Maria R.

Intel Customer Support Technician

[JonWay_C_Intel]

You may refer to the user guide:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_dev_specific_pdn_20.pdf

and also a training course....although it mentioned it is for Stratix3 and Stratix4, don't worry about it. The concept is the same.  

https://www.intel.com/content/www/us/en/programmable/support/training/course/opdn1100.html

After watching the above training course, you will find that ... overall, all you need is to feed the spreadsheet some info to find out what is your Ztarget and board info for the Feffective. Then, once you have that, it will populate a list of capacitor that can effectively reduce the impedance on your rail.