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Design Partition help

Mahdi
New Contributor I
271 Views

Hello all,

I have several questions regarding design partitioning in Quartus. What I am doing right now is to connect a custom IP core (let's call X) to a NIOS II and on-chip memory in my system. Also, I instantiated an FP custom instruction and a user-defined custom instruction and connected them to the NIOS.

My goal is to optimize (in terms of Fmax) each of these IP Cores in a separate project and then import them to my main project. Here are my questions:

 

1. Is it possible to have a design partition for the NIOS, on-chip memory, and other IP cores?

2. Why the Fmax drops when I try to have a design partition for the same design or when I want to have a logic lock region for my design?

Mahdi_0-1627224051721.png

 

3. Is it possible to instantiate a black box IP core in Platform Designer for those IP Cores, and then, import their partition database file in the main project? Let's say we have a partition database file for NIOS and X. I want to instantiate these IP cores in my main project but as a black box and then import their database file as a final snapshot. So, in this way, I can make sure that the Fmax will not drop when I connect them together. 

 

I am using Quartus Prime Pro v21.1, and Stratix 10

 

Thank you in advance for your help

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1 Solution
sstrell
Honored Contributor III
252 Views

1) Yes.

2) That depends.  It might be because the Logic Lock region is limiting the placement and routing options for the partition, so the performance is not as good as without the LL region.  If you don't need an LL region, don't enable it to give the Fitter more freedom.  However, with the design reuse flow that it sounds like you want to do, you would need an LL region to reserve a location for a design partition in another design.

3) Yes.  This is the design reuse flow.

See the block-based design user guide and associated training for details:

https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-pr...

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1 Reply
sstrell
Honored Contributor III
253 Views

1) Yes.

2) That depends.  It might be because the Logic Lock region is limiting the placement and routing options for the partition, so the performance is not as good as without the LL region.  If you don't need an LL region, don't enable it to give the Fitter more freedom.  However, with the design reuse flow that it sounds like you want to do, you would need an LL region to reserve a location for a design partition in another design.

3) Yes.  This is the design reuse flow.

See the block-based design user guide and associated training for details:

https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-pr...

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