I've implemented a OpenCL kernel and compiling it for two different FPGAs with two different amounts of ALMs, the compiler generates the same estimated resource usage:
; Estimated Resource Usage Summary
; Resource / Usage
; Logic utilization / 222%
; ALUTs / 146%
; Dedicated logic registers / 90%
; Memory blocks / 58%
; DSP blocks / 129%
One FPGA is the Cyclone V 5CSEBA6U23I7 from DE10-Nano board, with 41910 ALMs, 5662720 Memory Bits and 112 DSP blocks. I'm using the BSP for SDK OpenCL 18.1 downloaded from Terasic site.
The other FPGA is the Cyclone V 5CSEMA5F31C6 from DE1-SoC board, with 32070 ALMs, 4065280 Memory Bits and 87 DSP blocks. I'm using the BSP for SDK OpenCL 16.0 also downloaded from Terasic site.
Some BSP has a incorrect information that generates this same estimation, right?
Anyone knows how to solve this possible issue?
I was thinking of sending a e-mail directly to Terasic support, but first I would like to ask this question in their forums and the link in their site redirected me to here :)
The resources used by the BSP are listed in the board_spec.xml file located in the hardware/device directory of the BSP. (for example hardware/c10gx) It's possible Terasic forgot to update that file when creating the BSP. It's just a text file, so you can edit it if you want. However, the estimates shown using the -report option are very approximate. For a much better estimate, please use the report.html file.