Do ROM and/or Lookup Tables introduce an additional delay to the overall circuit?

[PSriv8]

I want to design a circuit in which a 5-bit input In[4:0] (ranges from 0 to 31) is associated with a corresponding 3-bit output Out[2:0]. I can design this using a 8x3 Encoder in which 5 out of 8 inputs can be connected to In[4:0] to provide the corresponding output, and other inputs (3 out of 8 inputs of encoder) can be set to 0. However, using an encoder will introduce an additional delay.

I can also use a lookup table (LUT) which has 32 locations. The 5-bit input In[4:0] can be used as the address for LUT and the storage size of LUT will be 3 bit to store the output Out[2:0]. The 3-bit output value can be stored in the LUT corresponding to the a given input.

My understanding is:

If we use a lookup table and store the data, the data will be available as soon as we provide the clock signal and it won't require additional delay like encoder.

Please suggest me whether to use an encoder or LUT if the main aim of the design is to reduce the processing time.

I am using a Cyclone IV device and Quartus software.

[sstrell]

An encoder is a logic structure constructed from LUTs (look up tables). They are not a different type of resource in the device. What you are thinking of in your second paragraph are the registers that are part of the LABs (logic array blocks) to store data.

So your question really is whether to implement your design as either a pure combinational logic structure (composed of just LUTs) or a synchronous design where outputs, generated from LUT logic, are stored in registers.

So the answer really depends on what you need. If your outputs are constantly monitored by whatever they are being fed to and whatever that is can process constantly changing inputs to your design (like just simple LEDs), the design can be purely combinational. In other words, your design is purely "sensitive" to the inputs because the outputs will immediately (after a logic gate delay) change if there is a change to the inputs. If you want to store the results of your design to prevent changes to them if there is a change or glitch on the inputs, you would need to have a synchronous design.

Neither solution is really a way of "reducing processing time" because the same logic is required to implement whatever function you create and the delay through that logic would be the same. The only difference is the outputs being available "immediately" or at the next clock edge. The "safer" solution is to register the outputs, creating a synchronous design.

Hope that helps.

#iwork4intel

[PSriv8]

Thank you for your reply.

I am actually designing an asynchronous circuit, in which the clock signal would be replaced by handshaking (REQUEST and ACKNOWLEDGEMENT) signals. Therefore the processing time of the asynchronous circuit depends upon the input unlike the synchronous design, in which the time period is calculated based on the worst-case or critical path delay. The no of clock cycles required by a given data is fixed, and that data can be either stored in an LUT or it can be designed using an encoder. The encoder would convert the input in no of cycle required or the same can be stored in LUT, and I need to choose the option which takes less processing time. What do you suggest?