Does Interface Templates option from Platform Designer > new component provides the RTL (verilog/vhdl) code apart from the skeleton hdl portlist?

[Sushmita]

Hi,

I was going through the following video about Avalon interface on platform designer. Regarding the same, the below points have been mentioned:

a) template option in new component can be used to get the signals and interfaces.

b) component_editor > files> create synthesis file from signals provides the top skeleton for the design.

My question is that does selecting the required template with proper parameters, provide the selected Avalon interface's RTL code after generating HDL in the platform designer?

Or does it provide only the top skeleton for the selected files?

Please find the link below:

Custom Component Development Using Avalon® and Arm* AMBA* AXI Interfaces

Refer from time 01 hr, 17 min in video:

https://www.youtube.com/watch?v=Vw2_1pqa2h0

[sstrell]

It's just the skeleton. You have to fill in the functionality. When you click "Create synthesis file from signals", you should see the template that you can then save and edit.

#iwork4intel

[Sushmita]

Okay.

Thanks for the reply.

[Sushmita]

Hi @sstrell​ 

I have found the templates for Avalon mm master and slave interfaces in .v format from the below given links. They are dated back to 2008. For example, mm master code provided in the zip file, uses FIFO,some control signals.

Can those templates be directly used in our custom modules as is to perform basic interface functionality or we have to customize the code as per used and unused signals?

LINKS:

1) master:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html

2) slave:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-memory-slave.html

[Kenny_Tan]

You may also take a look at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_avalon_verification_ip.pdf page 187 for testbench creation.

Thanks

[Sushmita]

HI,

Thanks for replying!

yes, I have seen the document. I have downloaded the zip file and opened in qsys.

But after following instructions as told in page 188, and i try to save changes, it shows that the example design is not writable. So i couldnt generate the HDl.

[Kenny_Tan]

what you need is just the content of the files. You can manually recreate the files and copy and paste the non writable files towards it.

[Kenny_Tan]

Any update?