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Downtrain to PCIe Gen3x8 when generating Quartus design with Avalon-MM+ IP for S10 GX dev kit

He4Forum
Employee
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Avalon® memory mapped Intel® Stratix® 10 Hard IP+ for PCI Express* Solutions User Guide shows that Avalon-MM+ IP can support Gen8 x 16 for PCIe.

He4Forum_1-1648446503899.png

When I genetate a design with the IP, I find there is a system message that says using Intel FPGA Root Comple BFM will downtrain design to Gen3x8.

He4Forum_2-1648446573047.png

Also when I test the design with S10 dev kit card, it seems the throughput for DMA, which is nearly 7GB/s, is based on Gen3x8.

How can I make the design still support Gen3x16?

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skbeh
Employee
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Hi sir

1) Please check to ensure your rootport CPU is also capable support up to gen3x16.

2) Instead of using the IP tab generated example design, please try use this Example Design from AN 881: PCI Express* Gen3 x16 Avalon® Memory Mapped (Avalon-MM) DMA with DDR4 SDRAM and HBM2 Memories Reference Design

Below is the document and design link:

https://www.intel.com/content/www/us/en/docs/programmable/683291/current/introduction.html


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He4Forum
Employee
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Hi skbeh,

I notice that the design you shared to me is for Intel® Stratix® 10 MX FPGA Development Kit, while I am using Intel® Stratix® 10 GX FPGA Development Kit. So will this cause any issue?

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skbeh
Employee
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Hi He Xu

Stratix 10 MX devkit OPN is 1SM21BHU2F53E1VG, while Stratix 10 GX devkit OPN is 1SG280LU2F50E2VG, both are using different device OPN.

Since you are using Stratix 10 GX devkit DK-DEV-1SGX-L-A, the AN881 example design cannot directly being used in your devkit, unless port over the pin assignments.


The design that you currently tested is generated from the 'Generate Example Design' tab as shown in screenshot below, correct?

By default this generated example design is only Gen3x8, have you modify the design to gen3x16? If no, then the link is gen3x8 only.


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skbeh
Employee
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Hi He Xu

Sorry please ignore the previous reply. I noticed you are using AvMM+ IP for PCI Express and generated the gen3x16 example design.

To determine if your example design is link-up as Gen3x8 or Gen3x16, kindly use Signaltap to monitor the value of currentspeed_o[1:0] and lane_act_o[4:0]


currentspeed_o[1:0] indicate the current speed of the PCIe link. The following encodings are defined:

2'b00 : Undefined

2'b01 : Gen1

2'b10 : Gen2

2'b11 : Gen3


lane_act_o[4:0] indicate the number of lanes that are configured during link training. The following encodings are defined:

5'b0 0001 : 1 lane

5'b0 0010 : 2 lanes

5'b0 0100 : 4 lanes

5'b0 1000 : 8 lanes

5'b1 0000 : 16 lanes


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He4Forum
Employee
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Hi skbeh,

 

Sorry, I am a newbie for Quartus Software. Do you mean I should use the Signal Tap Logic Analyzer?

He4Forum_0-1649823741404.png

 

After I clicked on the Signal Tap, it shows like this.

He4Forum_1-1649823818957.png

 

Then what should I do to monitor the value of currentspeed_o[1:0] and lane_act_o[4:0] as you told me?

Thanks.

 

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skbeh
Employee
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currentspeed_o[1:0] will indicates the link speed, i.e. Gen1, Gen2 or Gen3, see the definition in previous note.

lane_act_o[4:0] will indicates the link width, i.e. x1, ,x2, x4, x8, x16, see the definition in previous note.


In between, please check your board DIP switch SW2 setting, make sure SW2.4 is set to ON position (enable pcie x16).


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