I have a MAX10 Development Kit (https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/max-10...) that has 2 ethernet ports, both of which I'm trying to get working in linux on a Nios II core.
- I've got the linux part done using a rocketboards guide (https://rocketboards.org/foswiki/Documentation/AlteraMAX1010M50RevCDevelopmentKitLinuxSetup) but running iplink only returns a single port. To investigate, I unpacked the max10_devkit_ghrd.par file from the rocketboards guide and noticed that the project only utilizes a single port.
- My next thought was to either modify the Triple-Speed Ethernet IP Core to accommodate more ports, but that requires changing the IP core to not use a FIFO, which in hand changes the signals to the point where I don't know what goes where. (Included are before/after screenshots of system interconnect/qsys)
- Next I tried duplicating the Triple-Speed Ethernet IP Core, but that won't work because 2 cores would need to be tied to a single ENET_MDC, ENET_MDIO pin.
- I've also tried all of the example projects included with the MAX10 development kit, but none of them use >1 ethernet port.
- I know once I'm able to program the FPGA with both ports I will still need to modify the device tree, but that is an entirely seperate problem
Does anyone know of any reference designs, tips, or ideas on how to get both ethernet ports integrated with a Nios II core?
It's unlikely you can find exact complete reference design that connect to 2 Ethernet ports and with NIOS CPU. Hence, some form of design modification is still required.
I do able to find out below application note that showcase implementation of multiple channels of TSE IP core usage. Although this is Arria 10 reference design but the TSE IP core is the same. You can check it out and hopefully find something useful in it.
I have not hear back from you.
I hope the reference design that I shared with you can provide some guidance to you.
For now, I am setting this case to closure.