there is a newer release version of this board layout/schematics?
thank you for the feedback.
My question was related to the strange MIPI TX assignment used in this board. It seems that the MIPI TX interface is only connected to DIFFIO_RX pins, instead of DIFFIO_TX capable ones.
Is that a specific design constraint (e.g., lack of spare IOs) or do we need to follow this design to achieve the best performance?
The MIPI IP solution is developed by third party company called Foresys hence Intel is not familiar with the MIPI IP solution implementation detail.
The reference design link is as below
If you are interested with the MIPI IP solution detail, can check with Foresys directly via email@example.com
We have not heard from you and I hope that my last note clears up this matter. If you don’t have any further question, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.