FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

EK-10M50F484 release version

luca5
Beginner
166 Views

Hi

there is a newer release version of this board layout/schematics?

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-ma...

Thank you

0 Kudos
4 Replies
AR_A_Intel
Employee
153 Views

Hi

 

Welcome to INTEL forum. Based on my understanding, we don’t have newer release version. The latest is provided in web.


luca5
Beginner
145 Views

Hi,

thank you for the feedback.

My question was related to the strange MIPI TX assignment used in this board. It seems that the MIPI TX interface is only connected to DIFFIO_RX pins, instead of DIFFIO_TX capable ones.

Is that a specific design constraint (e.g., lack of spare IOs) or do we need to follow this design to achieve the best performance?

Thank you

AR_A_Intel
Employee
135 Views

Hi

 

The MIPI IP solution is developed by third party company called Foresys hence Intel is not familiar with the MIPI IP solution implementation detail.

The reference design link is as below

https://fpgacloud.intel.com/devstore/platform/18.1.0/Standard/mipi-csi2-rxtx-with-passive-d-phy/

If you are interested with the MIPI IP solution detail, can check with Foresys directly via ip@foresys.com


AR_A_Intel
Employee
117 Views

We have not heard from you and I hope that my last note clears up this matter. If you don’t have any further question, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Reply