I have ported a customer design from a competitor chip to an Intel FPGA and in doing so I have had to make a 'converter' from their interface to the DDR controller they originally had into an Avalon Memory mapped equivalent to read/write data to/from the EMIF block.
This is working fine but the throughput efficiency is not high enough.
Their interface is basically lots of 'bursts' of single write/read of data to consecutive addresses. For example this might look like 128 single writes of data on Avalon with a burst of 1 to consecutive addresses.
The data is only being accepted into the EMIF Avalon interface at roughly 1/4 of the Avalon clock rate (ready is not high most of the time).
My questions is this. Is the EMIF controller clever enough to spot that these multiple, single writes to consecutive address can be concatenated to a burst ? If not, if I rewrote the converter code to make the accesses Avalon Burst accesses (so for example one write of 128 burst length rather than 128 writes of burst length 1) would that make the interface to the EMIF much more efficient ?
My intuition says yes but my customer is in a hurry and I just wanted to know if any of you out there could confirm this or not before I invest the time to make it happen?
Any thoughts or advice much appreciated
As for the memory controller efficiency sequence address is the most efficiency pattern and random is not. When you issue the single write or read order the controller does not know if they are sequence address or not. Therefore the longer burst length is always the better efficiency you can get.
Here is the Avalon mm interface spec