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Honored Contributor I

EP3C120 + Nios2UDPOffloadExample

My apologies, I am utterly confused. Here is what I am trying to do... 


I have the Altera DSP Development Kit, Cyclone III Edition. 


I am using the Data Conversion HSMC to get data from the ADC to the board. 


Once I have the data on the board I want to send it via Ethernet to the PC. Process it. And Send it back to the board. 


Then ultimately back to the HSMC to a DAC. 


Basically Data from the board to a PC via Ethernet, and back. (the rest I should be able to deal with) 


I have been using the Nios2UDPOffloadExample. Everything compiles and I seem to have the example working, however I am unable to completely verify as it requires two boards. 


I can ping from the PC to the board. 


Right now I have a few Questions and would kill for any help (as I am currently beating my head against a wall and would like this done by monday) 


1) How do I select which IP the board tries to talk to? 

2) How do I select the port that the board tries to talk over? 

3) How do I send my own data? (I can make a simple LUT to cycle through for testing but how do I connect it? 


Any help would be much appreciated! 



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3 Replies
Honored Contributor I

Have a look at the source code. The CPU can configure the hardware to talk to a specific IP/port number, or receive packets with a specific destination port number. 

To send your own data, replace one of the packets generators by your own component.
Honored Contributor I

Daiziwen, thanks for the response. 


I am sorry it took so long to get back I had to spend some time trying to understand this code base. 


I currently have everything in Quartus and Nios II Tools for Eclipse. I found where I can change the IP address (and it is now set to but I still can't find packet generation. I see stuff that says packet generator is both the VHDL and C but nothing that actually looks like it is generating anything. 


Any help there? I figured my next step was to get it to send a simple count or "Hello World"
Honored Contributor I

The packets are generated using two IP blocks, called prbs_packet_generator and udp_payload_inserter. They are written in Verilog, and also have C drivers. 

In the application, have a look at demo_tasks.c. It calls the drivers to start the packets generation.