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As the FPGA(EPF6016QC240-3) powered up with 5V, am curious about the output voltage levels from the FPGA, are they going to be 5V outputs too ?
Atleast from datasheet it shows they will be at 5V level outputs(Pls refer attachment).
I could not find PIN out document for the FPGA EPF6016QC240-3?
Can you pls clarify both queries ?
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Hi,
Since this is legacy devices, I do not have much information to share here.
However, I found the device pin out information. Please refer to the link below for the pinout of the device:
Below link of the relevant documentation of the device:
Link Copied
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Hi,
Since this is legacy devices, I do not have much information to share here.
However, I found the device pin out information. Please refer to the link below for the pinout of the device:
Below link of the relevant documentation of the device:
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Hi,
there's more information about Voh in the datasheet, see Figure 18:
According to the diagram, Voh doesn't comply with 5V CMOS Vih requirements. Notices that there's only 5V TTL but no 5V CMOS Voh spec in operation conditions. It's most likely possible to raise Voh with an external pull-up resistor.
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Thank you for sharing the replies.
With the pin out information, I understand the device has the VCCIO pins, in the design as we used 3.3V for the VCCIO pins, it's obvious to have the output voltage levels aligned to the same voltage level, which would be 3.3V.
Thank you
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