- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Team
Can you please provide Electrical and Switching characteristics of CLKXX pins of Arria V FPGA?
Regards
Srikanth Kacchu
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Srikanth Kacchu
Sorry for late response.
Below is the doc (Section 1.1 and 1.2) that listing the Electrical and Switching characteristic:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_51002.pdf
Can you let us know if the doc is helpful?
Thanks.
Eng Wei
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Srikanth Kacchu
We do not receive any response from you to the previous reply that we have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi
1. What are the rise time, duty cycle, fall time and jitter specifications of CLK input/output and IO input/output signals?
2. Switching characteristics are provided for Transceiver signals only in section 1.2.
Regards
Srikanth Kacchu

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page